IN Brief:
- CEA-Leti has demonstrated 22nm FeRAM using vertically integrated hafnium zirconium oxide ferroelectric capacitors.
- The 1T-1C bitcells operate at 1.3V and have been reported down to 0.047µm².
- The technology targets embedded non-volatile memory for edge AI, HPC, aerospace, defence, and IoT platforms.
CEA-Leti has demonstrated ferroelectric RAM scaled to the 22nm manufacturing node using a 3D capacitor architecture based on hafnium zirconium oxide thin films.
Presented at the VLSI Conference in Honolulu, the work addresses a density barrier that has limited FeRAM’s ability to compete with volatile embedded memory. By integrating ferroelectric capacitors vertically rather than laterally, the research team produced memory cells reported to be 2.5 times smaller than standard SRAM at the same 22nm node, while retaining data without power.
FeRAM is attractive because it combines fast operation, non-volatility, and low-voltage potential, but its scaling has been constrained by capacitor area. In conventional planar structures, the capacitor can dominate the bitcell footprint because the current flowing through it during operation is relatively low. Shrinking the selection transistor does not remove that limit if the capacitor itself still consumes the area budget.
CEA-Leti’s 3D approach builds the capacitor upwards, increasing effective ferroelectric surface area within a tighter lateral footprint. The team demonstrated two back-end-of-line integration schemes for 3D ferroelectric capacitors at 22nm. Array functionality was confirmed down to 0.047µm² 1T-1C FeRAM bitcells operating at 1.3V, using a standard logic selector and a 3D ferroelectric capacitor with an aspect ratio of roughly 4:1.
The research also showed a route towards still higher density using 3D FeCaps with an aspect ratio of 17:1, 60nm diameter, and 120nm pitch. That structure reduces the capacitor footprint to 0.0028µm². The higher aspect ratio increases effective capacitor surface area within each bitcell, enlarging the memory window without sacrificing array density.
Reliability behaviour is another central element of the work. Traditional FeRAM devices can exhibit wake-up, in which electrical characteristics shift during early cycling and affect stability. CEA-Leti’s high-aspect-ratio 3D capacitors showed wake-up-free behaviour, consistent with an approximately 80% orthorhombic phase fraction in the HZO film, confirmed by precession electron diffraction. Confinement inside narrow vias appears to alter local strain and stabilise the ferroelectric crystal phase from the beginning of operation.
The memory development aligns with wider European work on FD-SOI and embedded non-volatile memory. A related FD-SOI collaboration between CEA-Leti and GlobalFoundries spans embedded memory, RF, power management, biomedical wearables, and 3D integration through the FAMES pilot line. The FeRAM result gives that platform activity a clearer memory-scaling path at the device level.
Embedded memory is becoming one of the harder constraints in edge compute. AI inference, sensor fusion, robotics, medical wearables, industrial monitoring, and defence electronics all require local storage close to processing hardware. Moving data repeatedly between memory, processor, and cloud infrastructure increases energy use, latency, and exposure to connectivity limits. Dense embedded non-volatile memory offers a route to storing model parameters, configuration data, and state information closer to the compute core.
SRAM remains fast and deeply integrated into logic processes, but it is volatile and increasingly expensive in area. Flash offers non-volatility, although integration and scaling constraints restrict some embedded use cases. FeRAM has occupied a narrower space because density has limited its competitiveness, even where its speed and endurance characteristics are useful. A 3D HZO capacitor architecture at 22nm gives it a stronger claim in systems where energy, standby power, and local data retention carry more weight than the smallest possible front-end logic node.
Aerospace and defence systems add further pressure because energy use, operating environment, and reliability are tightly controlled. Non-volatile embedded memory can preserve state, reduce boot dependencies, and support low-power operation in platforms where maintenance access or energy supply is limited. High-performance computing and edge AI systems face a different but related constraint: the cost of moving data can dominate the cost of processing it.
CEA-Leti plans to integrate the high-aspect-ratio ferroelectric capacitors into dense FeRAM arrays on a 22nm FD-SOI platform. The next step will test whether cell-level gains translate into manufacturable arrays with controlled variability, retention, endurance, peripheral circuitry, and design-rule compatibility. The development does not displace SRAM, but it sharpens FeRAM’s role as a credible embedded non-volatile memory candidate for low-power local compute.
