IN Brief:
- Analogue Insight is opening customer engagement for IKAIKA45GTX and IKAIKA45GRX IP in GlobalFoundries’ 45SPCLO platform.
- The transmitter and receiver support 1–32Gbps per lane and can be scaled into multi-lane optical interconnect designs.
- The IP targets co-packaged optics, silicon photonics, AI infrastructure, quantum photonics, and high-speed optical interconnect systems.
Analogue Insight has opened early customer engagement for low-power transmitter and receiver IP designed in GlobalFoundries’ 45SPCLO silicon photonics platform.
The London-based analogue and mixed-signal IP company is offering early evaluation and customisation for the IKAIKA45GTX transmitter and IKAIKA45GRX receiver. The IP supports 1–32Gbps per lane and can be supplied as a matched transmitter and receiver pair or as individual macros. Tape-out is targeted for the first quarter of 2027.
Designed for integrated co-packaged optics, the transmitter and receiver are intended to sit alongside electronics and photonics on the same die. Multi-lane implementations can support aggregate data rates such as 256Gbps and 512Gbps, depending on lane count and system architecture. Customer engagement before tape-out allows lane count, reach, and power budget requirements to be reflected before the design is frozen.
The baseline design is approaching completion at 32Gbps per lane. Target applications include co-packaged optics, silicon photonics, quantum photonics, AI infrastructure, and next-generation optical interconnect systems. The company’s wider focus spans analogue, mixed-signal, and high-speed interconnect IP and chiplets for advanced semiconductor designs.
GlobalFoundries’ 45SPCLO process is a 45nm SOI silicon photonics platform that supports monolithic integration of RF, analogue, digital, and photonic circuits. That combination is increasingly important as optical engines move closer to processors and switches. Co-packaged optics reduces the physical distance between electronic switching and optical transmission, but it also places tighter demands on interface power, channel reach, equalisation, clocking, and packaging.
AI infrastructure is the main pressure point. Large accelerator clusters need wider and more efficient data movement between compute, memory, and network fabric. Electrical interconnect faces energy and signal-integrity penalties as bandwidth rises, particularly when data must travel across boards, cables, and rack-scale topologies. Co-packaged optics aims to reduce those penalties by moving optical conversion closer to the silicon doing the switching.
The surrounding semiconductor platform is becoming as important as the optical device itself. Work on secure European semiconductor manufacturing flows has shown how foundry process choice now carries security, traceability, and jurisdictional weight alongside technical capability. In silicon photonics, the process platform also defines which electronic and photonic functions can be integrated without losing power efficiency or design practicality.
Analogue and mixed-signal IP remains one of the harder parts of that integration problem. Digital blocks can often be reused across projects with more predictable tooling, while high-speed interfaces must be tuned around channels, parasitics, power domains, noise, photonic device behaviour, and package layout. A transmitter or receiver that reaches a target line rate in isolation still has to work inside an optical engine where thermal, mechanical, and electrical compromises are already tight.
The UK has growing activity in specialist analogue and mixed-signal design, including related moves in analogue IC design capability. Such design services and IP blocks form a less visible layer of the electronics supply chain, but they become decisive wherever systems rely on high-speed links, low-noise interfaces, precision timing, or energy-sensitive data movement.
Opening customer engagement before tape-out is a practical step in a market where system fit can dominate raw specification. Lane count, clocking schemes, reach requirements, equalisation strategy, and test access all vary between co-packaged optics architectures. Early input gives customers a chance to shape the macro around the optical engine rather than adapting the system around a fixed interface later.
The commercial challenge will be proving the power, integration, and bring-up advantages once silicon is available. Co-packaged optics will advance when the optical, electrical, thermal, and packaging elements produce a complete system gain. Analogue Insight is entering that design window early, where mixed-signal decisions can still shape architecture rather than being forced into a late-stage compromise.
