IN Brief:
- Agile Analog and Xiphera are combining analogue anti-tamper sensor IP with digital cryptographic IP.
- The collaboration targets semiconductor security as post-quantum cryptography moves into hardware design roadmaps.
- Chip security increasingly has to cover both remote cryptographic threats and physical attacks against silicon.
Agile Analog and Xiphera have announced a collaboration that combines analogue anti-tamper sensor IP with digital cryptographic IP cores for semiconductor security.
The work brings Agile Analog’s agileSecure anti-tamper sensor IP together with Xiphera’s hardware-based cryptographic IP, including post-quantum cryptography capability. The intended architecture protects semiconductor devices at both digital and physical levels, pairing quantum-resistant cryptographic logic with real-time analogue glitch and tamper detection.
Chris Morrison, VP product marketing at Agile Analog, said: “As the industry prepares for the post-quantum era, we can no longer afford to view digital cryptography and physical security as separate silos.”
The collaboration addresses a security gap that becomes more visible as cryptographic algorithms are upgraded for a post-quantum environment. Quantum-resistant algorithms can protect data and communications against future cryptanalytic threats, but they do not automatically protect the underlying device from voltage glitching, fault injection, invasive probing, clock manipulation, or other physical attacks against silicon.
Agile Analog’s contribution centres on configurable, process-portable analogue security IP that can detect physical manipulation or abnormal operating conditions. Xiphera brings digital cryptographic cores, including post-quantum algorithms designed for hardware implementation. The combined approach gives SoC developers a route to build security subsystems that monitor the physical operating environment while protecting data paths and authentication mechanisms.
Tommi Lampila, CRO at Xiphera, said: “Customers look for trusted technology partners that can provide solutions for multiple layers of security architecture.”
That layered approach is becoming central to semiconductor security because encrypted communications are only one part of device protection. Chips used in industrial control, data centres, telecoms, defence, space, automotive, medical systems, and critical infrastructure often hold keys, authenticate firmware, secure boot processes, manage trusted execution, or protect sensitive workloads. If an attacker can manipulate the silicon physically, cryptographic strength alone may not preserve system security.
Post-quantum cryptography is adding urgency to those design choices. The migration from classical public-key algorithms to quantum-resistant schemes affects software, firmware, hardware security modules, secure elements, processors, FPGAs, and custom silicon. Hardware implementations must balance performance, side-channel resistance, area, power, latency, integration effort, and long-term update strategy.
Long-service design pressure has already been explored through coverage of lifetime design and FPGA-based post-quantum cryptography, where products were examined against operating conditions that change after release. Agile Analog and Xiphera are addressing the same problem at IP level, where security decisions made before tape-out can determine whether a device remains defensible years later.
The analogue side is particularly relevant because physical attacks exploit the real behaviour of silicon. Voltage, clock, temperature, electromagnetic conditions, and fault injection can all be used to disturb execution or extract secrets. Anti-tamper sensors provide local awareness of abnormal conditions, allowing the device to trigger protective responses such as reset, alarm, key zeroisation, or secure-state transitions.
The digital side carries different constraints. Post-quantum algorithms can be larger and more computationally demanding than some classical schemes, and hardware implementation has to account for throughput, area, power, latency, side-channel protection, and integration with existing security architectures. Xiphera’s cryptographic IP targets that implementation layer rather than leaving PQC solely to software.
Integration burden will influence adoption. Security IP has to fit into bus architectures, power domains, clocking schemes, test flows, debug restrictions, manufacturing provisioning, and firmware handshakes. A protection subsystem that is strong in isolation but awkward to integrate can create schedule risk or uneven deployment across product families.
The collaboration reflects a wider move from separate security blocks toward system-level protection. Cryptography, tamper detection, secure boot, lifecycle management, debug control, key storage, and update mechanisms increasingly have to operate as a connected architecture. As post-quantum cryptography moves from standards work into implementation, secure semiconductors will need defences that extend beyond the algorithm and into the physical behaviour of the chip itself.
