Xiphera joins Finnish secure SoC programme

Xiphera is joining Finland’s SecureSoC project, a three-year programme led by Tampere University to develop secure system-on-chip technologies for critical digital systems.

The €6.7m collaborative development programme is funded by Business Finland and brings together Insta, Nokia, VLSI Solution, Wapice, Xiphera, and TTTech Flexibilis. It builds on Finland’s earlier SoC Hub work, combining semiconductor design, hardware security, software, system integration, verification, and lifecycle protection within a national development framework.

SecureSoC is focused on SoC architectures for critical sectors including industry, defence, automation, and connected infrastructure. The project uses a security-by-design approach, with work covering digital and analogue components, AI-assisted verification, reusable IP integration, OpenTitan links, and system-level security evaluation.

Xiphera will contribute hardware-based cybersecurity and cryptographic IP to the programme. Its work will support the integration of cryptographic acceleration and security functions into next-generation Finnish semiconductor architectures, helping to build trusted foundations into the chip rather than adding protection solely at software or system level.

The wider partner group brings complementary technical strands. VLSI Solution contributes compact SoC and RISC-V processing expertise, Nokia is applying AI to design and verification through virtual environments and digital twins, Wapice is working on quantum-secure cybersecurity for edge devices and software lifecycle protection, and TTTech Flexibilis adds networking and time-sensitive communication expertise.

Security has shifted from software compliance into semiconductor architecture. Connected industrial systems, defence platforms, energy assets, medical technology, and telecoms infrastructure increasingly depend on embedded trust anchors, secure boot, cryptographic hardware, tamper response, and protected update mechanisms. Those functions are difficult to bolt on late without increasing cost, power, complexity, and verification burden.

The EU Cyber Resilience Act is also raising expectations for connected products placed on the European market, while post-quantum cryptography is forcing long-lifecycle equipment manufacturers to think beyond present-day cryptographic assumptions. SecureSoC brings those pressures into the design phase, where hardware roots of trust, cryptographic cores, and lifecycle provisioning can be planned as part of the SoC architecture.

Xiphera’s collaboration with Agile Analog on combining physical anti-tamper sensor IP with post-quantum cryptographic cores sits close to the same engineering problem. Physical attack detection and mathematical protection are converging because secure silicon has to resist both remote compromise and direct hardware manipulation.

The programme also touches a wider semiconductor sovereignty question. Access to secure IP, trusted development flows, and verified architectures can be as important as access to wafer fabrication, particularly for countries and regions building specialist semiconductor ecosystems around critical infrastructure, telecoms, industrial control, and defence applications.

The main trade-off will be architectural discipline. Secure roots of trust, hardware cryptography, secure lifecycle control, and tamper response all consume silicon resources and verification time. Designing them in early can reduce downstream exposure, but it also requires security, analogue, digital, software, and system teams to work from a shared model rather than a sequence of isolated design handovers.

SecureSoC gives Finland a structured route to develop that capability across industry and academia. Xiphera’s role strengthens the hardware-security layer of the programme, while the broader consortium points to a European semiconductor model built around trusted architectures, reusable IP, and resilient supply chains rather than volume manufacturing alone.