IN Brief:
- AuraStack extends Cadence’s agentic AI architecture into PCB and advanced-package development.
- The platform coordinates planning, constraints, routing, manufacturability, and multiphysics analysis.
- Continuous electrical, thermal, and mechanical feedback is intended to reduce late-stage design rework.
Cadence has introduced an agentic AI platform that coordinates PCB and advanced-package development from initial system planning through physical implementation, analysis, and sign-off.
AuraStack AI Super Agent operates within Allegro AI Studio and directs specialist agents across constraints management, physical structure definition, IP reuse, placement, routing, design for manufacturability, and multiphysics analysis.
The platform is connected with the Celsius thermal solver, Clarity 3D electromagnetic solver, Sigrity signal- and power-integrity environment, and MSC Nastran and Marc mechanical-analysis tools. Electrical, thermal, stress, vibration, drop, and fatigue behaviour can consequently be evaluated within a coordinated workflow.
NVIDIA Blackwell hardware and CUDA-X libraries accelerate the computational work. Cadence has specified potential productivity increases of up to 15 times and a reduction in time to market of up to half, although realised improvements will vary with design complexity, tool integration, reuse, and the quality of the underlying constraints.
AuraStack follows the ChipStack, InnoStack, and ViraStack systems addressing semiconductor design, verification, and package development. Its addition extends the architecture to the board and product level, where package selection, component placement, power delivery, cooling, mechanical loading, and manufacturability converge.
Early users and collaborators include NVIDIA, TSMC, Socionext, FORVIA HELLA, and Schneider Electric. Cadence plans to make the system available during 2026.
In one FORVIA HELLA workflow, AI-assisted placement reduced a task involving 300 components from as much as four days to four minutes. Such acceleration can create additional time for examining alternative layouts, although final verification and production qualification remain necessary.
TSMC has also reported productivity increases of up to 100 times for substrate auto-routing developed through its collaboration with Cadence, with output quality described as comparable with manual routing. Advanced packages containing several dies, dense interconnect, and high-current power networks provide a natural target for that level of automation.
Design closure crosses engineering boundaries
PCB development can no longer be isolated cleanly from package, thermal, mechanical, and enclosure engineering. High-current distribution affects copper geometry and temperature, package routing alters signal integrity before the board trace begins, and mechanical constraints can invalidate an otherwise satisfactory electrical placement.
Sequential analysis often exposes those conflicts late. A layout may pass an electrical review before thermal modelling identifies an unacceptable hot spot, while a mechanically convenient component position can create a difficult high-speed route or restrict airflow elsewhere in the enclosure.
Continuous multiphysics feedback shortens the distance between a design change and its consequences in another domain. The agentic layer adds orchestration by gathering constraints, initiating analyses, examining results, and proposing subsequent actions across several specialised tools.
The same architecture is already being applied to autonomous semiconductor design and verification workflows. Board and package development introduces additional variability through materials, suppliers, stack-ups, manufacturing tolerances, mechanical loading, and cooling conditions.
Traceability will determine whether automated decisions can be accepted within qualified development processes. A generated layout change must retain the applicable constraints, tool versions, solver assumptions, and result history so that a reviewer can reconstruct why it was made.
An agent can optimise the metric available to it without improving the wider system. Reduced routing length may worsen thermal concentration, while a lower-cost component substitution can alter availability, lifecycle, or power integrity, requiring the orchestration layer to balance objectives rather than pursue one result in isolation.
Manufacturing information must remain equally controlled. Stack-up capability, via rules, assembly tolerances, test access, component availability, and supplier-specific process limits can change during development, and an automated workflow will propagate outdated inputs as efficiently as valid ones.
Institutional knowledge offers both an opportunity and a risk. Capturing proven rules, layouts, and known failure modes can make specialist experience available across a larger team, while poorly documented exceptions or obsolete practices may be reproduced across several programmes.
Computational demand will influence how continuously the analysis can run. Large advanced packages and dense AI systems require substantial electrical, thermal, and mechanical simulation, so teams may still separate rapid exploratory checks from formal sign-off runs using higher-fidelity models.
AuraStack changes the speed at which alternatives can be created and assessed, rather than removing engineering responsibility from the process. Its industrial value will depend on whether automation remains explainable, reproducible, and compatible with the evidence required for design review and production release.
