IN Brief:
- HELIX is a four-year research programme between STMicroelectronics and the National University of Singapore.
- Work will cover in-memory computing, accelerator architectures, embedded memory, and system-to-silicon integration.
- Researchers will use ST's P18 18nm FD-SOI platform with embedded phase-change memory.
STMicroelectronics and the National University of Singapore have opened a four-year semiconductor research laboratory focused on reducing the memory, power, and integration constraints facing more capable edge-AI systems.
The ST-NUS HELIX Corporate Lab will work across AI algorithms, accelerator architectures, memory systems, circuits, chip integration, and silicon implementation. HELIX stands for Hardware for Embodied Low-power Intelligent Xcceleration and is intended to support generative and embodied AI operating locally on physical systems.
Research will focus on memory-centric architectures, in-memory computing, heterogeneous accelerators, and scalable combinations of compute and storage. ST is providing a dedicated design chassis built around its P18 18nm fully depleted silicon-on-insulator technology and embedded phase-change memory.
The choice of memory architecture is deliberate. AI processors can perform large numbers of arithmetic operations efficiently, but repeatedly transferring model weights and intermediate data between logic and separate memory devices consumes energy and introduces latency.
Bringing storage closer to compute, or performing selected operations within memory structures, reduces some of that traffic. The benefit depends on workload, memory capacity, precision, and architecture, but data movement is now a substantial part of the power budget in many edge-AI systems.
ST’s P18 FD-SOI platform gives HELIX an industrial semiconductor process on which those ideas can be implemented. FD-SOI supports body biasing, allowing designers to adjust device behaviour as operating requirements change, while embedded phase-change memory provides non-volatile storage alongside the on-chip SRAM hierarchy.
Laurent Malier, executive vice-president of Global Technology R&D at STMicroelectronics, said: “ST’s strength as an integrated device manufacturer lies in our ability to bring together advanced silicon technologies, embedded memory, circuit design, heterogeneous integration and chiplets.”
The programme extends beyond standalone inference accelerators. Embodied AI covers robots, drones, and other physical systems combining sensing, local computation, and real-time actuation, where cloud connectivity may be too slow, intermittent, or power-hungry for the entire control loop.
That creates a tighter system budget than conventional data-centre AI. Compute performance has to coexist with battery capacity, enclosure volume, cooling, sensor interfaces, deterministic response, and often several communications links inside the same platform.
HELIX is intended to address those constraints from the model level down to the silicon. NUS researchers will contribute work in integrated circuits, computer architecture, AI models, and system design, while ST supplies process technology, embedded memory, integration capability, and semiconductor engineering support.
The dedicated design chassis should also shorten the less glamorous part of semiconductor research: rebuilding infrastructure before a new accelerator idea can be tested. Researchers will have a common industrial implementation platform on which to integrate and validate new blocks rather than treating every project as a separate chip foundation.
That can expose architectural weaknesses earlier. A concept that performs well in software or FPGA emulation may behave differently when mapped onto a particular process with finite memory density, interconnect delay, leakage, analogue constraints, and realistic power delivery.
Edge AI is already pushing designers towards more heterogeneous hardware. CPUs, neural accelerators, DSPs, embedded non-volatile memory, SRAM, interfaces, and security functions increasingly have to coexist on one device or tightly integrated package.
The attraction of chiplets and heterogeneous integration is that each function does not necessarily have to be manufactured on the same process. The penalty is a larger design problem around die-to-die links, power, thermal behaviour, software partitioning, packaging, and test.
HELIX will use its four-year programme to examine those trade-offs through working implementations rather than limiting the research to model simulations. Its output is expected to include research platforms and demonstrators, not an immediately commercial processor family.
The useful test will be which memory, accelerator, and integration concepts remain attractive after they have been placed onto industrial silicon. Edge AI has no shortage of proposed architectures; fitting enough compute, memory, and sensing into a practical power budget is the part that tends to expose them.
