Silicon Line launches 20Gbps MIPI SerDes

Silicon Line launches 20Gbps MIPI SerDes

Silicon Line has launched a dual-port 20Gbps MIPI SerDes chipset. The architecture extends camera links over optical fibre or differential copper while limiting interconnect power in constrained imaging systems.


IN Brief:

  • MSDL 20G combines the SL8582x serializer and SL8581x deserializer with two 10Gbps links.
  • Optical implementations can extend MIPI D-PHY over tens of metres, with differential copper supporting shorter links.
  • Sampling and evaluation kits are available for machine vision, medical, robotics, and other multi-camera systems.

Silicon Line has introduced a dual-port 20Gbps MIPI D-PHY serializer/deserializer chipset designed to extend high-bandwidth camera connections over optical fibre or differential copper while keeping SerDes power below 100mW per 10Gbps link.

The MSDL 20G is the first device family in the company’s MIPI Serial Data Link range and combines the SL8582x serializer with the SL8581x deserializer. Each component supports two ports, allowing two simultaneous 10Gbps serial links to carry camera or display traffic between sensors and more distant processing hardware.

The design addresses a familiar limitation in multi-camera systems. MIPI D-PHY is widely used as a short-reach interface between image sensors and processors, but extending those connections through a robot, industrial machine, medical instrument, or other distributed system raises signal-integrity, electromagnetic-interference, harness-weight, and power-consumption problems.

Silicon Line converts the MIPI traffic into serial links suitable for fibre or copper transport. The company specifies optical reach of tens of metres, while differential electrical connections can operate over shorter distances of around two metres. That allows sensor modules to retain a native MIPI interface even when the main compute hardware cannot be positioned nearby.

The SL8582x accepts up to four MIPI D-PHY data lanes per port together with the associated clock lane. Individual D-PHY lanes can run at up to 2.5Gbps, giving each port an aggregate payload of 10Gbps and the dual-port device a combined 20Gbps capability.

Power consumption is a significant part of the design. Silicon Line specifies typical combined serializer and deserializer consumption of 71mW per optical link and 87mW in electrical mode, excluding the integrated sideband SerDes. Those figures are important where several cameras are distributed through small enclosures with limited airflow or thermal mass.

Heat generated by the interconnect can become a design constraint in its own right. Medical imaging heads, robotic sensor assemblies, and compact machine-vision systems may already contain image sensors, illumination, power conversion, and local processing close to their thermal limits. Reducing SerDes dissipation leaves more of the available thermal budget for the functions that directly determine system performance.

The chipset also includes a bidirectional sideband link for lower-speed control and peripheral traffic. I²C, GPIO, SPI, digital audio, sensor clocks, and related signals can share the same general connection architecture, reducing the number of separate conductors that must run between a remote camera and the host electronics.

Optical transport offers a further advantage where electromagnetic compatibility is difficult. Fibre removes the conductive path between endpoints and avoids the susceptibility of copper cabling to strong electrical fields around motors, switching power electronics, and other noisy equipment. Copper remains available where the link is shorter and the cost or complexity of optical conversion is unnecessary.

Silicon Line is targeting industrial robotics and machine vision alongside medical imaging, defence, UAV, AR, and VR systems. The applications differ, but each can require multiple high-resolution sensors feeding central processing electronics at data rates that make the physical connection increasingly important.

The chipset is sampling in bare-die form and in compact 4mm by 4mm µBGA-78 packages, with evaluation kits available for design validation. That gives engineering teams a route to characterise reach, optical or electrical performance, thermal behaviour, and camera compatibility before committing the parts to a production platform.

As imaging workloads become more distributed, sensor performance is only useful if the data can reach the processor reliably and within the available power budget. MSDL 20G is aimed squarely at that less glamorous part of the system architecture, where an unsuitable interconnect can erase much of the benefit delivered by the camera and compute silicon at either end.


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    Silicon Line has launched a dual-port 20Gbps MIPI SerDes chipset. The architecture extends camera links over optical fibre or differential copper while limiting interconnect power in constrained imaging systems.