Orthogone opens low-latency FPGA networking IP

Orthogone Technologies has made its ultra-low-latency FPGA networking IP portfolio available to engineering teams beyond the financial trading applications for which much of the technology was originally developed. The package targets AMD UltraScale+ and Versal adaptive platforms and combines Ethernet, protocol offload, and host data-movement functions intended for deterministic networked systems.

The Ethernet MAC and PCS range covers 1G, 10G, 25G, 40G, and 100G line rates. Reed-Solomon forward error correction is available on selected 25G and 100G implementations, while separate TCP/IP and UDP/IP offload engines move transport-layer processing into FPGA logic. A PCIe DMA controller provides bidirectional movement between the programmable device and host memory over Gen3 and Gen4 interfaces.

Orthogone says the IP has been deployed and refined in production FinTech systems over several years, where predictable latency and low jitter are central requirements. The company is now targeting applications including aerospace and defence, telecommunications, high-performance computing, industrial systems, test equipment, and quantum computing.

The common design problem across those markets is determinism rather than bandwidth alone. A general-purpose processor and software network stack can move large volumes of traffic, but operating-system scheduling, cache activity, interrupts, buffering, and queueing can vary the time taken to process individual packets. For systems responding to external events within a defined timing budget, variation can matter as much as the average transfer rate.

FPGA logic provides an alternative by placing packet handling into a fixed hardware path. Ethernet framing, protocol processing, filtering, timestamping, or application-specific functions can be carried out without repeatedly handing data through a host software stack. The result can reduce both latency and jitter, although it shifts more of the implementation burden towards hardware design, verification, and integration.

Orthogone’s portfolio addresses several stages in that path rather than offering a single network interface block. MAC and PCS cores provide the physical Ethernet-side processing, TCP and UDP engines can remove protocol work from the CPU, and the PCIe DMA controller transfers resulting data between FPGA logic and host memory. Used together, the blocks can form much of the data plane for a SmartNIC or a specialist embedded communications subsystem.

The company publishes a round-trip figure below 585ns for the PCIe DMA controller on one documented host configuration. That number is useful as a reference point but should not be treated as the latency of a complete application. Host hardware, PCIe topology, memory access, FPGA implementation, packet size, software, and whatever processing occurs before and after the accelerated path will all affect end-to-end performance.

Orthogone is also supplying the surrounding development material needed to put the cores into use. The package includes encrypted RTL, AMD Alveo reference designs, simulation testbenches, Linux drivers, libraries, APIs, and documentation. That supporting layer matters because a low-latency hardware core can save little development time if each customer has to build the host interface, verification environment, and software integration from the beginning.

UltraScale+ and Versal platforms give designers room to combine the communications path with application-specific processing on the same programmable device. Incoming data can therefore be parsed, filtered, transformed, or acted upon before the host CPU sees it. Removing unnecessary crossings between devices can reduce latency further, but it also makes FPGA resource use, timing closure, memory architecture, and maintainability part of the system-level decision.

The expansion beyond FinTech will test how transferable the IP is between markets with different lifecycle and qualification requirements. Aerospace equipment may demand long support periods and environmental verification, while industrial and communications platforms can place greater emphasis on interoperability and field maintenance. Quantum computing control systems present another set of timing and interface constraints.

Orthogone is making the portfolio available for evaluation and licensing now. The engineering proposition is less about reproducing financial-trading architectures in unrelated markets than applying the same deterministic network path where software variability has become a system constraint. Whether that provides enough advantage to justify an FPGA implementation will depend on the complete data route, but the portfolio gives designers a set of pre-developed building blocks for making that assessment.