TI adds high-speed telemetry and 800V protection ICs

Texas Instruments has introduced a 3GSPS analogue-to-digital converter, an isolated 800V hot-swap controller and a bulk acoustic wave oscillator for AI data centre hardware. The three devices address separate engineering problems: finding short disturbances on power rails, controlling the insertion of loads into high-voltage distribution and providing stable timing for high-speed communications.

The ADC34DSO75 samples at up to three gigasamples per second and combines conversion with on-chip digital signal processing. TI is positioning it for event-based, remote monitoring of low-voltage, high-current power rails, where a short voltage disturbance may occur between readings from a slower management system. Capturing such an event provides information about the waveform and its timing rather than simply a longer-term average voltage.

Remote monitoring can reduce the need to install a laboratory oscilloscope at the point of a sporadic fault. The ADC processes samples to identify transient events, allowing diagnostic information to be reported without treating the entire high-speed sample stream as conventional continuous telemetry. Precisely what can be stored, how triggers are configured and how captured events reach host software must nevertheless be checked against the device documentation and the implementing system.

Capturing a glitch accurately also depends on the analogue signal path ahead of the converter. The sensor and analogue front end must have sufficient bandwidth, appropriate input range and controlled noise, otherwise a fast ADC will measure a distorted version of the disturbance. Trigger choices also determine which events are recorded. No independently measured reduction in data centre failures or downtime has been established for installations using this converter.

The LMI800PS addresses a different fault mechanism on the distribution side. It combines an isolated bias supply and PMBus telemetry with hot-swap control for 800V DC and split ±400V power architectures. According to TI, the integration replaces a reference solution requiring five integrated circuits and reduces the necessary board area by more than 60%. The board-area comparison is against that specified implementation, not a universal reduction for every competing design.

As a load is connected to an energised DC bus, its input capacitors can demand a substantial charging current unless the power path is controlled. A hot-swap controller manages insertion and responds to electrical faults so that a single branch need not disturb other equipment on the common bus. The controller still forms part of a broader protection circuit, including appropriately rated switching devices, current sensing and upstream isolation; the complete system’s fault behaviour cannot be inferred from the controller alone.

TI specifies 5kVrms reinforced isolation and more than 8mm creepage for the LMI800PS. These characteristics help separate control and communication circuitry from a hazardous power potential, while insulation coordination and equipment approval remain responsibilities of the finished design. The device complements 800V rack conversion developments, whose semiconductor power stages regulate voltage rather than manage connection and fault isolation on the shared distribution path.

The LMK6B supplies a stable reference clock using a bulk acoustic wave resonator. TI advertises 9.6 femtoseconds of jitter at 625MHz, although the figure requires a measurement qualification. For an AC-LVPECL output at 625MHz, TI specifies 9.6fs typical RMS with a 4MHz high-pass filter, compared with 18fs over the stated 12kHz to 20MHz integration range without that filter. Results also depend on output format and the integration bandwidth used.

Clock phase noise can translate into timing uncertainty in the transmit and receive circuits of fast serial links. A low-jitter reference helps preserve timing margin, but the bit error rate of a deployed network interface also reflects its serializer, channel loss, equalisation and receiver performance. The oscillator figure therefore describes a component under defined measurement conditions rather than the guaranteed quality of an entire multi-terabit connection.

TI is demonstrating the components at the Open Compute Project Global Summit in San Jose. Board evaluation will need to establish trigger thresholds for transients and input bandwidth for the ADC, coordinated bus protection around the hot-swap controller, and jitter performance under the intended clock integration bandwidth. TI has not published results from a combined operational data centre deployment.