IN Brief:
- Silicon One G302 is a 51.2T top-of-rack switch ASIC with 200G SerDes interfaces.
- Cisco associates the new platform with 1.6T optics and direct-to-chip liquid cooling.
- G302 shipments are targeted before the end of 2026; G300-based systems are already shipping.
Cisco has expanded its Silicon One semiconductor portfolio with the G302, a 51.2T switching device designed for top-of-rack networking in dense AI computing installations. The chip uses 200G serializer/deserializer interfaces and is intended to support equipment using 1.6T optical connections. Cisco expects the G302 to begin shipping to customers before the end of 2026, while systems based on the previously announced G300 have already started shipping.
A top-of-rack switch aggregates connections from servers and accelerator equipment before forwarding traffic into the wider network fabric. The bandwidth available between that switch and its optical modules is a limiting part of the electrical design, particularly as equipment migrates to denser 1.6T interfaces. Cisco’s 200G SerDes is intended to support that local interface requirement, allowing high-rate serial data to pass between the ASIC and surrounding connectivity hardware.
Serializer/deserializer circuitry transforms data into high-speed electrical streams and reconstructs it at the receiver. At 200G signalling rates, channel attenuation, reflections, crosstalk and jitter all consume signal margin. Package escape routing, printed circuit board materials, connector choice and the transceiver electrical interface become interdependent design decisions. The nominal SerDes rate does not guarantee that every installed port will sustain an identical useful data rate under all traffic conditions.
Cisco specifies 51.2T of aggregate switching capacity for the G302, with 1.6T optics used in the associated systems. Those figures describe different levels of the design: total ASIC switching bandwidth and the class of optical connection. Real port counts, forward-facing bandwidth and possible oversubscription depend on how the switch manufacturer allocates the silicon’s lanes. A complete G302 port map and production benchmark have not been disclosed.
Cooling also becomes part of the semiconductor integration problem at these densities. Cisco associates the G302 platform with direct-to-chip liquid cooling, which carries heat away from components through a liquid-cooled assembly rather than relying solely on air flow. Heat instead passes from the chip package through thermal interfaces to the cooling assembly; coolant remains within its specified liquid circuit. Heat transfer depends on the package, thermal interface materials, cold plate, liquid circuit and the operating power of the installed system.
Pluggable transceivers, signal-conditioning electronics and the switch ASIC each contribute to the local thermal load, while cable access limits the positioning of cold plates and service clearance. Cisco has not published a G302 chip-level power figure or a comparable system energy measurement.
The wider Silicon One range has a different commercial status. The previously announced G300 is a 102.4T device and is available for customer sampling, while the first G300-based systems are shipping. These milestones do not apply to the newly introduced 51.2T G302, for which Cisco is targeting customer shipments before the end of 2026. The company also says P200-powered systems are already deployed in hyperscale production environments.
Integration requires more than the announced switching capacity: line-card layout, optical module compatibility, firmware, network operating software and environmental testing all have to be qualified. Even platforms within one semiconductor family may use different port densities, cooling arrangements and deployment schedules.
Separately, Cisco and NVIDIA plan to develop an Ultra-Dense Small Form Factor Pluggable (USFP) optical specification. The proposed design targets 400Gb/s per electrical lane and up to 12.8Tb/s aggregate capacity. It remains a proposed multi-source specification, with connector geometry, electrical compatibility and interoperability yet to be established across suppliers; no G302 implementation has been demonstrated.
The semiconductor advances also have to meet practical board-level constraints. As lanes grow faster, the allowable insertion loss across substrate, board trace and connector typically becomes harder to manage; pushing more data through a smaller switch footprint also changes power distribution and thermal design. Those physical limits explain why a nominal switching-capacity increase does not translate directly into an equivalent gain in usable rack bandwidth.
Cisco presented the G302 during the Open Compute Project Global Summit on 12 October. The company’s next stated milestone is to begin customer shipments before the end of 2026, after which deployed systems can provide firmer evidence of realised throughput, interoperability and thermal performance.
