TSMC’s 2nm process reaches 8% of wafer revenue

Taiwan Semiconductor Manufacturing Company has reported that its 2nm process accounted for 8% of wafer revenue during the third quarter of 2026, providing a new measure of commercial production following the technology’s introduction into volume manufacturing. The figure was disclosed on 15 October alongside financial results showing substantial growth in revenue and earnings at the semiconductor foundry.

TSMC recorded consolidated revenue of NT$1,494.24bn for the three months ending 30 September, an increase of 50.9% from the corresponding period in 2025. Net income reached NT$763.06bn, up 68.7% year on year, while diluted earnings per share rose to NT$29.43. Gross margin was 66.4%, operating margin 58.7% and net profit margin 51.1%.

The technology breakdown provides a more specific indication of the foundry’s manufacturing mix. In addition to the 8% contribution from 2nm, 3nm processes accounted for 33% of wafer revenue, 5nm processes contributed 28% and 7nm represented 10%. Combined, technologies at 7nm and below generated 79% of wafer revenue during the quarter.

These figures concern wafer revenue, not the number of wafers processed or the company’s total consolidated revenue. Different process technologies command different prices and support products with widely varying die dimensions, manufacturing complexity and customer requirements. The revenue percentages therefore cannot be used to calculate physical wafer output or the number of functional semiconductor devices manufactured on each process.

TSMC’s N2 technology introduces a gate-all-around nanosheet transistor architecture, replacing the fin-based transistor structures used in its preceding leading-edge generations. In a conventional FinFET, the gate controls the conducting channel from multiple sides of a raised fin. A nanosheet device surrounds the channel more completely, allowing additional control over the electrical conditions governing transistor switching.

That control is particularly important as transistor dimensions become smaller. Continued scaling can increase the influence of leakage currents and unwanted electrostatic effects, making it harder to preserve useful switching behaviour while reducing operating voltage. The gate-all-around arrangement provides an additional means of managing these constraints, although transistor performance remains dependent on channel geometry, material characteristics and fabrication quality.

The nanosheet architecture also introduces manufacturing requirements beyond those of earlier FinFET processes. Multiple channel structures must be formed and controlled consistently, while deposition, etching and other fabrication steps need to maintain the intended geometry across the wafer. Small variations can affect the electrical characteristics of the completed transistors, influencing device performance, leakage and yield.

TSMC has described N2 as offering improvements in performance, power efficiency and transistor density relative to preceding technologies under defined conditions. The benefits obtained in a finished integrated circuit depend on how designers use those characteristics. A design may prioritise lower power consumption, higher operating frequency or additional functionality, while other limitations associated with memory, interconnects and packaging can restrict the system-level improvement.

Interconnect behaviour becomes increasingly important as logic devices are packed more closely together. Resistance and capacitance in the wiring between transistors can affect timing and energy consumption, even when individual switching devices become more efficient. Dense processors also require sufficient power delivery across the die, making electrical distribution and thermal management part of the physical design challenge.

These constraints influence the development of later process variants. TSMC has outlined enhanced technologies within its nanosheet roadmap, including N2P and A16. The latter introduces a backside power rail approach intended to change how electrical supply connections are routed through the device structure. Such developments represent additional process options and should not be treated as identical to the baseline N2 technology responsible for the newly reported revenue share.

Moving suitable power connections away from the front-side signal routing layers can free resources for interconnections between logic devices. However, implementing backside power delivery introduces further fabrication and integration requirements. The design must accommodate the additional processing steps and the electrical characteristics of the resulting connections without compromising manufacturing reliability.

Adoption of a new process also requires supporting design tools, validated semiconductor intellectual property and appropriate physical design rules. Standard-cell libraries, device models, memory interfaces and verification software must reflect the properties of the manufacturing technology. Design teams need to evaluate timing, power integrity and manufacturability against those models before committing a completed chip layout to production.

The rise of 2nm within TSMC’s revenue mix therefore reflects activity across a broader design and manufacturing ecosystem, rather than the introduction of a transistor architecture in isolation. Semiconductor products fabricated on the node depend on the availability of suitable tools, qualified circuit libraries, packaging options and production processes capable of delivering acceptable yield.

Wafer yield is another important distinction between revenue growth and manufacturing efficiency. Producing more wafers on an advanced process does not establish that every wafer contains the same number of usable devices. Defects, die dimensions and process variation influence the proportion of functional chips obtained, and TSMC has not disclosed an N2-specific yield figure in its third-quarter earnings announcement.

In US dollars, TSMC reported quarterly revenue of $46.72bn, representing an increase of 41.2% year on year. The different growth rates in Taiwanese dollars and US dollars reflect the currency basis used in the comparisons. The financial statements were prepared under Taiwan’s adopted financial reporting standards, with the reported results covering the quarter ending 30 September.

Wendell Huang, senior vice-president and chief financial officer, attributed the quarter’s performance to strong demand for leading-edge process technologies. Management expects that demand to continue through the fourth quarter, including a steep ramp-up of 2nm production. Its guidance anticipates revenue of $52.3bn to $54.3bn, with a gross margin of 65% to 67% and an operating margin of 56.5% to 58.5%.

Those fourth-quarter figures remain forecasts. The completed third-quarter results establish an 8% revenue contribution from N2 and a 79% contribution from the foundry’s four most advanced reported process generations. Subsequent disclosures will show how that balance develops as 2nm production increases and customers introduce additional devices using the technology.