Arteris passes 1,000 semiconductor design starts

Arteris has surpassed 1,000 confirmed customer silicon design starts using its interconnect intellectual property, with an analysis of those projects identifying substantial changes in AI processing, semiconductor complexity, and the demands placed on communication structures within chips.

The company recorded the milestone during the third quarter of 2026 and has published research comparing customer design activity across successive periods. Its report, The State of Semiconductor Innovation: Insights from 1,000 Design Starts, covers system-on-chip designs, application-specific integrated circuits, field-programmable gate arrays, and microcontrollers.

Arteris develops network-on-chip interconnect technology, system integration software, and hardware security assurance tools. Its interconnect intellectual property provides the communication structures used to transfer information between processing cores, accelerators, memory controllers, and other functional blocks within complex semiconductor devices.

As processing architectures become more specialised, the movement of data between these elements increasingly influences the performance of the completed chip. Adding computational resources does not produce a corresponding increase in useful processing capacity if the interconnect cannot supply information at the required rate.

A network-on-chip, or NoC, addresses this requirement through a communication architecture containing multiple connections and routing elements. Rather than relying entirely on a shared bus, the system can direct transactions between different parts of the semiconductor according to the available paths and the requirements of each connected function.

The interconnect must accommodate traffic with different characteristics. An accelerator performing large mathematical operations may require sustained access to high-bandwidth memory, while a control processor exchanges smaller messages with peripherals and other system functions.

These competing requirements affect routing, arbitration, latency, and power consumption. A design that meets its computational performance target in isolation can encounter bottlenecks when several processing blocks attempt to access the same memory resources.

Arteris estimates that NoC interconnects represent 10% to 13% of chip and chiplet area in the architectures examined. The proportion indicates the physical resources associated with data movement in those designs, although it is a company-reported figure rather than a universal measurement for all semiconductor devices.

The company’s historical records show a marked change in customer workloads. AI-related projects accounted for 4% of Arteris design starts during 2010–2014, rising to 50% during 2021–2025.

These figures describe the composition of Arteris’ customer projects, not the global proportion of semiconductor designs incorporating AI. They nevertheless demonstrate how the company’s interconnect business has developed alongside demand for specialised processors and accelerators.

AI hardware places particular pressure on memory access and data movement. An accelerator may contain many arithmetic units capable of performing operations concurrently, but those units require a continuous supply of input data and somewhere to store intermediate results.

Moving information between computing elements and memory consumes electrical power, while contention for communication resources can introduce delays. Semiconductor designers must therefore coordinate the interconnect architecture with memory hierarchy, processing capacity, and the physical arrangement of functional blocks.

Enterprise computing has also become a larger part of Arteris’ customer activity. Data centre, cloud computing, and high-performance computing applications accounted for 11% of design starts during 2010–2014, compared with 43% during 2021–2025.

These applications increasingly use custom silicon containing specialised acceleration, high-speed interfaces, and memory subsystems. Their architecture must support the movement of large amounts of information while maintaining suitable performance and power consumption across the completed device.

The growing adoption of chiplets introduces a further level of integration. Instead of manufacturing every function on one semiconductor die, a system can combine several dies within a package, potentially using different semiconductor processes for processing, memory, and interface functions.

That arrangement requires communication both within each die and between the dies. The system must account for interconnect bandwidth, latency, physical connections, clocking, and power delivery, while also accommodating the characteristics of the packaging technology.

Arteris has been developing products for these architectures, including FlexGen Multi-Die and Ncore Multi-Die. The technologies extend its interconnect portfolio to support communication across more complex semiconductor assemblies.

Automotive designs provide another example of increasing system requirements. According to the report, approximately two-thirds of Arteris’ automotive design starts carry an Automotive Safety Integrity Level-related classification, while nearly half combine functional safety requirements with AI capabilities.

Automotive electronic systems must manage faults according to their intended function and safety requirements. Communication structures can form part of the mechanisms used to protect data integrity, identify errors, and maintain appropriate separation between system functions.

Combining those requirements with AI processing increases the work involved in integration and verification. High-bandwidth acceleration must operate alongside control functions that may have different timing, diagnostic, and safety obligations.

Arteris also reports a ninefold increase in its measured design complexity over the preceding two years. The company has not provided a directly comparable industry-wide complexity measure, so the figure should be interpreted within its own design-start analysis and assessment methodology.

Greater architectural complexity can increase the number of interconnections that must be configured and verified before manufacturing. Semiconductor teams must establish whether separately developed intellectual property blocks exchange information correctly, maintain suitable timing behaviour, and operate within the intended security and power constraints.

The technical developments accompany stronger commercial activity for Arteris. The company reported third-quarter revenue of $25.8m, an increase of 48% year on year, while annual contract value plus royalties reached $103.8m.

Its historical design-start analysis provides a view of how customer requirements have changed as semiconductor development has moved towards AI accelerators, custom computing infrastructure, and increasingly complex multi-die systems. The next stage of those developments will depend on integrating greater processing capability without allowing communication, memory access, and verification demands to overwhelm the completed architecture.