Dismantled: February’s electronics bottlenecks moved further downstream

February 2026 did not deliver a single headline breakthrough that rewrote electronics engineering overnight. It did something more operationally useful — it clarified where performance is being won, where it is being rationed, and which parts of the value chain now carry leverage. The month’s defining pattern was a steady migration of constraint away from transistor counts and towards the adjacent systems that make modern silicon usable at scale: memory bandwidth, advanced packaging throughput, and power delivery that does not collapse into heat and copper loss.

The industry has been here before, at least in miniature. Every major compute cycle eventually runs into the unglamorous physics of moving electrons, moving data, and removing heat. What changed, and what February made harder to ignore, is the degree to which those constraints are now priced into corporate strategy, capex, and geopolitics. It is one thing for engineers to mutter about HBM availability and packaging queues; it is another for the market’s largest suppliers to publicly frame them as revenue engines and schedule risks.

Memory becomes a battleground

The clearest February signal came from the memory stack. Samsung’s update that it had started shipping HBM4 to customers, alongside performance figures and talk of HBM4E sampling later in 2026, was less about a single supplier’s roadmap than about the industry’s centre of gravity. In AI accelerators, memory bandwidth and latency have become the practical determinants of usable compute. A GPU or custom accelerator can promise teraFLOPs all day; if it cannot be fed, it spends its life waiting.

Design teams already understand this in architectural terms — wider buses, better interconnect, more aggressive caching, more careful partitioning — but supply reality has turned it into a systems constraint. HBM is not a drop-in BOM line. It is a yield story, a packaging story, and a qualification story, all of which sit uncomfortably close to the critical path for product launches. When a component becomes the throttle, the supplier landscape matters more, and the long tail of second-order effects — allocation, binning, integration support, and failure analysis capacity — starts to shape schedules as much as schematic decisions.

Advanced packaging is now a capacity market

February also put a number on something the industry has been performing in practice for years: advanced packaging is no longer a supporting act. ASE’s forecast that its advanced packaging business could double to roughly $3.2bn in 2026, together with commentary tying its subsidiary SPIL to AI-chip packaging supply, reads like the packaging sector finally being allowed to speak in the same commercial register as foundries.

For engineering and design teams, the implication is straightforward and uncomfortable. If your performance roadmap depends on 2.5D integration, high-density interposers, or increasingly complex multi-die assemblies, then your risk profile depends on packaging capacity, process maturity, and test strategy. The packaging house is not just the last stop before shipping. It is a point of failure that can determine whether you have product at all.

This is also where February’s story becomes about industrial structure. Advanced packaging is capex heavy, talent constrained, and prone to learning curves that do not compress simply because a customer is impatient. The acceleration of investment suggests confidence that demand will endure, but it also suggests that the bottleneck has moved to the part of the chain that historically had less visibility and, therefore, less forgiveness when something breaks.

3D stacking gets commercial

Broadcom’s announcement that it expects to sell at least one million chips by 2027 using stacked design technology is another marker of maturity. The report’s detail that Fujitsu is the first customer testing engineering samples, and that the manufacturing plan involves TSMC fabricating a 2nm die fused with a 5nm die, is particularly telling. This is not a research programme. It is a volume target, with a specific integration strategy that accepts heterogeneity as the point, not the compromise.

Heterogeneous integration is often discussed as an engineering inevitability — chiplets here, stacks there, a future of modular silicon. February’s shift is that companies are framing it as a commercial product category with an addressable market and a timetable. Once that happens, everything adjacent becomes less optional. EDA flows must cope with multi-die timing and power integrity in ways that do not collapse into heroic manual effort. Verification needs to address inter-die interfaces and fault containment. Thermal management has to move from a back-end concern to a first-order constraint. Test — always the quiet tax on complexity — becomes a competitive differentiator, because you cannot sell stacked volume if your yield analysis is a guessing game.

Materials and geopolitics keep biting

February also reminded the industry that the supply chain is not only about wafers and lithography tools. Reuters reporting on worsening shortages of yttrium and scandium affecting aerospace suppliers, and raising concern for semiconductor manufacturing, is a case study in how strategically annoying materials constraints can be. These are not the headline raw materials that get a mention in every commodity round-up. They are specialist inputs, often used in small quantities, which makes them easy to ignore until they are unavailable.

At the same time, export controls continued to evolve from political signalling into operational disruption. Reports of U.S. lawmakers pushing for tighter restrictions on China’s access to chipmaking tools, including servicing installed equipment, sit alongside accounts of China’s own expanding enforcement and the confusion exporters face in classifying controlled items. The engineering relevance is prosaic but serious: lifecycle support assumptions now carry policy risk. Qualification strategies and service contracts look different when a government can become an unplanned stakeholder in your maintenance schedule.

The industry has a habit of treating geopolitics as a background condition, something handled by legal teams and public affairs. That separation becomes less tenable when export controls and licensing decisions translate into delays, redesigns, and second-sourcing exercises that land back on engineering desks.

Manufacturing geography shifts, but time still wins

Foundry geography continues to diversify, and February added weight to that trend. TSMC’s comments around plans to mass produce 3nm chips in Kumamoto, Japan, alongside previously stated plans for 3nm production at its second Arizona fab in 2027, reinforces the direction of travel: advanced-node capacity is spreading beyond Taiwan. It is also a reminder that geography does not solve the calendar. New sites, new ecosystems, and new supply networks take time to stabilise, and early ramp is rarely the same thing as dependable volume.

For design engineering specialists and consultancies, that matters because qualification and resilience planning require lead time that product cycles do not always offer. A second source that arrives after the design has shipped is not a second source. It is a press release.

The creeping importance of connectivity

Away from the bleeding edge, February also offered a softer signal about mainstream electronics strategy. Texas Instruments’ agreement to buy Silicon Labs for roughly $7.5bn, framed around expanding TI’s wireless connectivity position alongside its analogue and embedded base, suggests that connectivity is being treated as a platform layer worth owning outright.

This is not purely an IoT story, nor is it only about RF IP. Connectivity increasingly drags in security obligations, software maintenance expectations, certification costs, and ecosystem support. Owning that layer allows a company to amortise engineering investment across industrial-scale volumes, while shaping how products are specified and integrated. It is vertical integration with a strategic intent: control the interfaces that determine long-term attachment, and you control more of the system than your silicon footprint alone would imply.

GaN grows up because the data centre demands it

If the compute stack was February’s visible drama, power conversion was its enabling subplot. Moves by suppliers such as ROHM to strengthen GaN supply capability, including deeper integration with TSMC process technology for an end-to-end production system, align with broader messaging from major power semiconductor players about GaN’s expansion into data centres and AI servers.

AI infrastructure is pushing power density and efficiency requirements into territory where incremental gains compound into usable capacity. When racks and clusters approach multi-megawatt scales, conversion losses become heat, and heat becomes cost, reliability risk, and, ultimately, a ceiling. GaN’s appeal is its ability to shift that equation — higher switching frequencies, better efficiency in certain regimes, and smaller magnetics — but its industrialisation is also a manufacturing story. As with HBM and advanced packaging, the question is no longer whether the technology works; it is who can build it at volume with predictable quality.

Regulation hardens into design requirements

Europe’s Cyber Resilience Act, with reporting obligations beginning in September 2026 and broader compliance deadlines in December 2027, continued to loom in the background, but February’s policy cadence makes it harder for product companies to treat it as a future problem. For electronics and design engineering, the practical effect is that security, vulnerability handling, patch support, and software bill of materials discipline begin to resemble core design constraints. They are not features. They are liabilities, with timelines.

The industry has long tolerated a split personality: hardware engineered for longevity, software shipped as a moving target, and security treated as something to be patched after the fact. The direction of travel in regulation suggests that split will become harder to defend.

Outlook: performance will be built by the supply chain that can keep up

February’s most consequential lesson is that electronics performance is being manufactured across a wider and less forgiving set of dependencies. Memory bandwidth, packaging integration, and power conversion have joined lithography as arenas where competitive advantage can be created — or lost. At the same time, materials constraints and export controls continue to add friction that no amount of clever architecture can fully erase.

For engineers, the challenge is not simply technical ambition. It is designing with an awareness that the system’s limits are increasingly external: capacity, qualification, serviceability, and compliance. The most advanced design is still a prototype if the supporting chain cannot deliver it.