IN Brief:
- Imec, ASML, and TSMC have demonstrated nFET and pFET 2D-material devices at 50nm contacted poly pitch on 300mm wafers.
- The process uses transition metal dichalcogenide channels, single-patterning EUV lithography, and a reverse thin-film transistor flow.
- The work strengthens the case for 2D-material logic in future ultra-scaled, back-end, and wafer backside applications.
imec, ASML, and TSMC have demonstrated a 300mm integration route for 2D-material transistors, producing scaled nFETs and pFETs with a 50nm contacted poly pitch.
Presented at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, the work brings atomically thin transition metal dichalcogenide channels into a process flow closer to industrial semiconductor assumptions. The nFETs use MoS2 as the channel material, while the pFETs use WS2 or WSe2, with both transistor polarities integrated on the same 300mm wafer.
Device integration has been one of the main barriers facing 2D-material transistors. Lab-scale devices have produced strong short-channel results, but larger contact areas and less production-relevant patterning have limited their value as scaling candidates. By reducing contacted poly pitch while retaining usable electrical behaviour, the partners have moved the discussion from material promise towards manufacturable device geometry.
The reported process delivered 94% operational transistors, measured as devices with an Imax/Imin ratio above 105. Both transistor polarities showed very low off current at zero gate voltage, while WSe2 pFETs performed close to the best reported lab-based devices. Those results are important because p-type TMD transistors have historically lagged n-type devices, complicating the development of complementary logic.
Single-patterning EUV lithography was used to support the scaled contacted poly pitch, with process optimisation carried out with ASML. The devices also use a reverse thin-film transistor flow, in which bottom contacts are created through pre-patterned tungsten-filled trenches before the TMD channel is transferred and a deposited overlapping gate is added. That sequence gives the contact and gate structures more compatibility with advanced wafer processing while reducing damage risks to the thin channel.
The development sits alongside growing work on heterogeneous integration, including related progress on III-V chiplet integration on silicon interposers. Both tracks reflect a broader movement away from relying on front-end transistor scaling alone. Device architecture, lithography, packaging, wafer backside functions, and interposer-level integration are now being developed as connected parts of the same performance roadmap.
Silicon logic still has several near-term routes forward, including gate-all-around devices, backside power delivery, buried power rails, chiplets, and advanced packaging. 2D materials remain a longer-horizon technology, but their attraction is clear: strong electrostatic channel control at very small dimensions, with potential use in ultra-scaled logic and additional transistor functions above or behind conventional silicon layers.
Europe’s semiconductor research base is increasingly visible in these transitions. Related work on a trusted European chip manufacturing flow addresses secure production and data handling, while imec’s 2D-material research tackles the physical device options that may shape later nodes. The two strands meet in the same industrial requirement: advanced electronics need platforms that can be designed, manufactured, verified, and scaled.
The next step is circuit-level proof under tighter variability and design-rule constraints. A promising wafer demonstration does not make production immediate, but 300mm integration, EUV patterning, complementary device polarities, and measurable yield behaviour bring 2D transistors into a more serious engineering frame. Future adoption will depend on whether those devices can support repeatable circuits, usable design kits, and integration routes that fit the economics of advanced manufacturing.
