IN Brief:
- Menta and Presto Engineering have formed a collaboration around embedded FPGA-enabled ASIC architectures.
- The work combines standard-cell eFPGA IP with ASIC design, qualification, and industrialisation support.
- Adaptive silicon is gaining weight as standards, security requirements, and field workloads change faster than hardware replacement cycles.
Menta and Presto Engineering have formed a strategic collaboration to accelerate adaptive ASIC architectures using embedded FPGA technology.
The agreement brings together Menta’s standard-cell-based embedded FPGA IP and Presto Engineering’s ASIC design and industrialisation capability, giving semiconductor developers a route to combine ASIC efficiency with a degree of hardware flexibility after deployment. The collaboration targets programmes in which algorithms, protocols, security requirements, or interface demands may shift during the product’s field life.
Presto Engineering becomes a select design partner for Menta, extending access to eFPGA IP through services covering ASIC design, validation, qualification, production ramp-up, and lifecycle support. That combination takes the concept beyond IP licensing and into the practical flow of bringing a configurable hardware block into manufacturable silicon.
Pure ASICs remain attractive where performance, power, integration, and unit cost dominate the design brief, but their fixed behaviour at tape-out leaves little room for late technical change. Discrete FPGAs preserve flexibility, although they can add board area, power consumption, cost, and supply-chain exposure. Embedded FPGA IP sits between those options by placing reconfigurable logic inside the ASIC itself.
The approach is suited to long-lifecycle systems used in industrial, aerospace, defence, communications, medical, and critical infrastructure equipment, where hardware often remains deployed well beyond the assumptions made during architecture definition. Security algorithms, communications standards, sensor interfaces, and control workloads can all change faster than equipment qualification or replacement cycles allow.
Menta’s implementation is based on standard-cell technology rather than proprietary hard macros, a distinction that can affect process portability, node selection, and foundry strategy. In markets where availability and longevity carry as much weight as peak silicon performance, the ability to move or reproduce IP across process technologies can be commercially significant.
Presto Engineering adds the manufacturing-facing discipline that adaptive ASIC projects require. Verification, test strategy, yield learning, packaging, qualification, production transfer, and supply-chain management all decide whether a flexible architecture becomes a deployable component. Reconfigurable logic inside an ASIC also needs to be validated as part of the wider device, rather than treated as a separate convenience block.
The same direction has already been visible in coverage of embedded reconfigurability and long-life silicon at Embedded World 2026, where adaptable hardware was linked to field change rather than laboratory novelty. Menta and Presto are now extending that theme into the ASIC industrialisation route, where commercial deployment depends on production discipline as much as architecture.
Configurable logic can be used for protocol adaptation, crypto agility, post-silicon correction, custom acceleration, sensor-interface variation, or product differentiation from a common silicon base. Used selectively, it can protect a larger ASIC investment from redesign when one function changes. Used poorly, it can add avoidable area and verification complexity, so architecture partitioning remains central.
ASIC economics are becoming more demanding as design costs rise and qualification cycles lengthen, while products are expected to support more software-defined operating conditions. The collaboration gives chip developers a route to bring adaptability inside the device, rather than adding flexibility externally through larger boards or secondary programmable devices.
Europe’s semiconductor position is often strongest where specialist IP, long-lifecycle design, industrialised ASIC services, and application-specific manufacturing knowledge intersect. Adaptive ASIC architectures will not replace fixed-function silicon, but they give engineers another option where field change is expected and hardware redesign would be expensive, slow, or operationally disruptive.
