IN Brief:
- Siemens and Samsung Foundry are extending collaboration around advanced-node design enablement.
- Work covers photonic verification, physical verification, DFT, yield analysis, advanced packaging, analogue, RF, and digital implementation.
- Foundry-aligned EDA flows are becoming central to first-pass silicon confidence at advanced nodes.
Siemens EDA and Samsung Foundry are extending their collaboration on advanced semiconductor design and manufacturing workflows for fabless chip developers.
The work spans Siemens electronic design automation software across design, verification, simulation, silicon manufacturing enablement, advanced packaging, and implementation flows. It was highlighted around Samsung SAFE Forum 2026, with the companies focusing on production-ready design enablement for Samsung Foundry process technologies.
Photonic integrated circuit verification is one part of the collaboration. Using Siemens Calibre software, the joint flow supports equation-based design rule checking, curvilinear layout-versus-schematic verification, and advanced pattern matching, helping photonic designs move through manufacturable process flows.
Physical verification and layout optimisation are also covered. Siemens’ Calibre nmPlatform tools are qualified for Samsung Foundry processes, while Samsung plans to release Calibre DesignEnhancer Pge for 2nm. The tool uses automated layout enhancement to address electromigration and IR drop through power-grid optimisation.
Siemens’ Tessent portfolio supports the design-for-test and yield-analysis portion of the work. Defect-oriented test strategies, physical failure analysis, and high-resolution chain diagnosis reference flows are being used to improve failure isolation on advanced-node silicon.
Advanced packaging adds another layer of complexity. Samsung Foundry is using Siemens tools to support its 2.3D Cube-E advanced package platform, with Innovator3D IC Integrator and Innovator3D IC Layout helping with early floorplanning, rapid design changes, and daisy-chain netlist generation for designs exceeding two million pins.
Analogue, RF, and library verification are being addressed through Siemens’ Solido Simulation Suite, including Solido SPICE, Analog FastSPICE, and Solido LibSPICE. The collaboration includes automotive qualifications on 4nm and 2nm, updated model support from 18nm through 2nm, and reliability analysis using Open Model Interface support.
Digital implementation work brings Aprisa software into the collaboration, with certification for Samsung Foundry leading-edge process nodes. Power, performance, and area closure remain central pressures as chips pull together logic, memory interfaces, analogue, RF, photonics, and advanced packaging inside tighter development schedules.
Automation is already reshaping analogue and mixed-signal design, as seen in Celera’s acquisition of SiliconGate. Siemens and Samsung are addressing the same pressure from the foundry-flow side, where implementation, signoff, reliability, packaging, and manufacturing constraints have to be visible far earlier in the design cycle.
As advanced chips grow more heterogeneous, first-pass silicon confidence is being built across the full design chain rather than at a single verification gate. Photonics, power integrity, DFT, yield, packaging, analogue behaviour, RF performance, and digital closure now interact too deeply to be treated as isolated stages.
Foundry-certified EDA flows reduce uncertainty at the tape-out boundary, particularly for AI, automotive, communications, and high-performance computing devices where advanced-node access is costly and re-spins are difficult to absorb. The collaboration gives chip teams a more coherent route from architecture through implementation, signoff, packaging, and manufacturing.
