IN Brief:
- The tie-up brings French research institutes and Taiwanese foundry capability together around next-generation AI packaging.
- RISC-V compute IP, silicon photonics, and microLED optical links are being targeted at PSMC’s 3D stacking and interposer platforms.
- The collaboration points to a broader shift in AI chip design, where bandwidth and power efficiency increasingly depend on heterogeneous integration rather than process shrink alone.
CEA-Leti, CEA-List, and PSMC have formed a collaboration aimed at pushing optical interconnects and open processor IP deeper into advanced AI packaging, combining silicon photonics, microLED-based optical links, and RISC-V with PSMC’s 3D stacking and interposer platforms.
The move targets a problem that has become increasingly difficult to ignore in AI hardware: compute blocks are scaling faster than the links that feed them. As bandwidth demands rise, conventional copper interconnects bring power, thermal, and signal-integrity penalties that become harder to manage inside densely integrated packages. The new programme is designed around short-reach optical communication for chiplet-to-chiplet data movement, alongside RISC-V compute blocks that can be tuned for workload and power targets rather than locked to a fixed processor roadmap.
That makes the partnership notable less as a stand-alone research exercise than as an extension of a broader packaging direction already visible inside PSMC. The Taiwanese foundry unveiled its 3D AI Accelator platform in 2023, combining 40nm logic and 25nm DRAM in a wafer-stacked architecture built to increase bandwidth while cutting power and cost. A further collaboration with Soitec in 2025 pushed into ultra-thin substrate and transistor-layer-transfer work for nm-scale 3D stacking, suggesting that PSMC’s roadmap is widening from memory-logic integration towards more heterogeneous AI packages.
Olivier Thomas, deputy head of the digital IC design division at CEA-List, said, “RISC-V is transforming processor design by combining openness, flexibility, and cost efficiency.” In this programme, that processor flexibility is being paired with photonic chiplet communication so customers can target specific performance and energy envelopes without relying entirely on bleeding-edge logic nodes to do the heavy lifting.
CEA-Leti is placing particular emphasis on microLED as the optical engine inside the collaboration, using low-power GaN light sources to increase short-reach optical throughput within advanced packages. That points to an architecture in which optical links are not treated as a board-level add-on, but as part of the package itself, helping move high volumes of data between tightly coupled dies without pushing electrical interconnects further into their efficiency limits.
For PSMC, the attraction is clear. Advanced packaging has become one of the most contested parts of the AI semiconductor stack, and mature-node economics are increasingly being paired with heterogeneous integration to find performance gains outside a straight race to smaller geometries. If the collaboration yields foundry-ready IP blocks and process flows, it could give customers another route into AI accelerators and supporting silicon that depends less on process shrink alone and more on packaging, interconnect efficiency, and workload-specific compute design.
