IN Brief:
- Siemens has introduced Solido Characterizer for semiconductor library characterisation.
- The tool combines predictive AI with Solido LibSPICE to increase characterisation throughput.
- Library generation is becoming a larger constraint as process corners, margins, and LVF requirements expand.
Siemens Digital Industries Software has introduced Solido Characterizer, an AI-powered tool developed to accelerate semiconductor library characterisation across mature, advanced, and emerging process nodes.
The software forms part of the Solido Characterization Suite and targets the generation of SPICE-based Liberty files used by digital implementation and sign-off tools. Siemens says the system can deliver up to seven times greater throughput, reducing Liberty file generation from weeks to days by combining predictive AI with Solido LibSPICE, a purpose-built AI-accelerated characterisation simulator.
Library characterisation is one of the less visible stages of chip development, but digital design tools depend on it throughout implementation and sign-off. Timing, power, noise, and variation models all have to describe how cells behave across different process, voltage, and temperature conditions. As margins tighten and designs move across more operating points, characterisation workloads grow quickly.
Solido Characterizer uses predictive AI technologies to accelerate creation of those models while retaining SPICE-based accuracy as the reference foundation. The tool is also integrated with Solido Analytics, giving engineering teams access to quality assurance, resource monitoring, and interactive debugging while characterisation jobs are running.
The software was shown at Siemens’ User2User Europe event in Munich and is available now. It is aimed at foundries, IP providers, and in-house chip teams producing or verifying libraries for standard cells, I/O, memories, and custom cells. The wider Solido suite supports Liberty data types and structures including NLDM, CCS, LVF, timing, power, noise, and variation.
Electronic design automation is absorbing AI in increasingly specific parts of the design flow. Verification, simulation, debug, layout optimisation, and model generation are all under pressure as SoCs become larger and process variation becomes harder to manage. Cadence’s autonomous AI work in chip verification reflects the same industry movement from general engineering assistance towards AI-supported production workflows.
Characterisation brings a distinct technical challenge because a library is only useful if downstream tools can trust it. A faster model-generation process still has to support timing closure, power analysis, noise checking, variation-aware optimisation, and sign-off confidence. Advanced formats such as Liberty Variation Format add the statistical detail needed for modern designs, while also increasing the number of simulations and model checks required before a library is ready.
Siemens’ approach pairs predictive AI with a purpose-built simulator rather than treating AI as a replacement for established electrical analysis. That balance is becoming central to EDA adoption. Engineering teams can benefit from acceleration, screening, and guided exploration, but production flows still need traceable results that connect back to recognised simulation methods.
AI is also moving through Siemens’ broader engineering software portfolio. The addition of PhysicsAI to the Simcenter simulation flow applied reduced-order AI models to speed CFD-based design exploration. Solido Characterizer takes the same broad direction into IC design, where AI is being used to reduce the cost of exploring large model spaces without discarding the engineering discipline behind simulation.
Foundries and design teams now have to support more process variants, more IP blocks, more application-specific silicon, and more customer-specific requirements. Library readiness can therefore become a tape-out constraint rather than a background task. Shortening that process can improve IP availability, reduce schedule friction, and help teams manage the modelling burden attached to advanced and highly customised designs.
Adoption will depend on production confidence rather than benchmark acceleration alone. Chip teams have little room for tools that save time early in the flow while adding uncertainty at sign-off. If Solido Characterizer can shorten characterisation while maintaining model quality, it gives semiconductor teams a direct route to reduce one of the practical bottlenecks in the IC development cycle.
