IN Brief:
- RISC-V Summit Europe 2026 is running in Bologna from 8 to 12 June.
- The programme covers embedded systems, AI, automotive, HPC, security, space, and software enablement.
- Europe’s open-hardware ecosystem is moving towards production-ready tools, profiles, and silicon.
RISC-V International, the University of Bologna, and Planning are hosting RISC-V Summit Europe 2026 in Bologna, bringing manufacturers, researchers, public institutions, academics, students, and technology suppliers together around the open instruction set architecture.
The event runs from 8 to 12 June at the Palazzo dei Congressi, with the main summit programme taking place from 9 to 11 June. Sessions cover embedded systems, AI, automotive, high-performance computing, security, space, software enablement, and open hardware research.
Bologna gives the summit a strong European research base. The University of Bologna has been central to RISC-V work through the PULP research platform and is a key partner in TRISTAN, the EU Chips Joint Undertaking initiative focused on expanding and industrialising Europe’s RISC-V ecosystem.
The programme shows how RISC-V has moved beyond architectural interest and into system deployment. Sessions include low-power AI for smart glasses, RISC-V for open physical AI, matrix extensions for AI workloads, security isolation mechanisms from microcontrollers to confidential computing, and RISC-V use in space and sensing applications.
Hardware profiles are expected to play a significant role in the discussions, particularly as RVA23-compliant silicon starts to give software and hardware developers a more predictable target. Standard profiles reduce the risk that RISC-V’s openness becomes fragmentation, helping toolchains, operating systems, verification environments, and commercial silicon to converge around stable implementation classes.
That discipline is essential as RISC-V moves into production embedded systems. Open architectures give silicon designers room to customise processors around workload, power, cost, and security requirements, but product deployment depends on the surrounding software stack, debug infrastructure, validation methods, and long-term support.
Safety-related RISC-V software has already become a more active development area, with HighTec and SiFive linking qualified compiler tooling with processor IP for automotive and industrial use. The Bologna summit reflects the same movement at ecosystem level, where open hardware has to be matched by credible software, verification, and certification routes.
Europe’s interest in RISC-V also sits inside a wider semiconductor sovereignty push. Open instruction set architectures give companies and research institutes greater control over processor design, yet sovereignty depends on much more than ISA access. IP quality, EDA tools, manufacturing routes, packaging, security assurance, software maturity, and lifecycle support all determine whether open hardware becomes a deployable industrial platform.
RISC-V’s strongest near-term opportunity may be in areas where customisation is more valuable than simple processor substitution. Edge AI, robotics, vehicles, satellites, sensors, industrial controllers, and secure embedded systems all need processors shaped around power, determinism, integration, and long service lives.
The Bologna summit presents RISC-V as a maturing engineering ecosystem rather than a research slogan. Its next stage will be measured through deployable silicon, stable toolchains, production-grade verification, and support models that can carry products through qualification and field use.
