IN Brief:
- HighTec and SiFive are combining qualified compiler tooling with RISC-V processor IP for safety-critical automotive and industrial systems.
- The collaboration supports Rust and C/C++ development using LLVM-based toolchains qualified up to ISO 26262 ASIL D.
- The work strengthens the software ecosystem needed to move RISC-V into certifiable, long-life embedded products.
HighTec EDV-Systeme and SiFive are working together to support safety-ready RISC-V software development for automotive and industrial systems, pairing qualified compiler technology with processor IP intended for long-life, certification-heavy applications.
The collaboration combines HighTec’s LLVM-based Rust and C/C++ toolchains with SiFive’s RISC-V processor IP, giving software teams a more coherent route into safety, security, performance optimisation, and scalable embedded development. HighTec’s toolchain is qualified according to ISO 26262 up to ASIL D and also supports cybersecurity development aligned with ISO 21434.
As RISC-V moves beyond early evaluation boards, software maturity is becoming one of the decisive barriers between architectural interest and production deployment. Automotive and industrial developers need more than processor openness; they need qualified tools, traceable workflows, security evidence, long-term support, and confidence that compiler behaviour will stand up to certification review.
HighTec’s support for hybrid Rust and C/C++ development addresses a practical software transition now emerging across embedded systems. Existing automotive and industrial platforms still carry large C and C++ codebases, yet new safety and security expectations are creating room for Rust in selected modules where memory safety, maintainability, or vulnerability reduction justify its introduction.
SiFive’s automotive-focused RISC-V IP brings scalable processor performance with safety and security functions built into the architecture. Combined with HighTec’s qualification kit and compiler support, the collaboration reduces the amount of integration work normally required when teams assemble a safety-critical RISC-V development environment from separate suppliers.
The work follows a broader pattern across the RISC-V ecosystem, where processor IP, compilers, real-time operating systems, and development tools are being pulled into more integrated safety propositions. MIPS and Green Hills have taken a similar route around safety-certified RISC-V development, while Semidynamics and SiPearl have pushed open architectures further into European high-performance computing infrastructure.
For industrial control, robotics, vehicle electronics, power conversion, and edge systems, the software environment has to support deterministic behaviour across years of maintenance and multiple product variants. Tool qualification and compiler confidence therefore sit close to the hardware decision, rather than arriving as a late-stage compliance task.
RISC-V’s appeal remains strongest where customisation, supply-chain flexibility, and architectural control carry commercial value. Its adoption in safety-critical systems, however, depends on whether suppliers can offer development routes that look familiar to engineers already working under functional safety rules. By bringing qualified compilers and processor IP into a closer working model, HighTec and SiFive are addressing one of the less glamorous but more decisive parts of the RISC-V production stack.
