IN Brief:
- Imec has added system-level integration features to its 300mm RF silicon interposer platform.
- The platform combines III-V chiplets with Si-CMOS, high-density MIMCAPs, RF passive modelling, and laser-assisted bonding.
- The work targets mmWave, sub-THz, and high-speed data-centre systems where packaging, passives, and RF interconnect increasingly define performance.
imec has advanced its 300mm RF silicon interposer platform with high-density embedded capacitors, RF passive-component modelling, and laser-assisted bonding for the heterogeneous integration of III-V chiplets on Si-CMOS.
The Leuven research hub is developing the platform for high-frequency systems in which compound semiconductors such as InP, GaAs, and GaN are combined with the scale and cost structure of silicon CMOS. The architecture keeps performance-critical functions in compact III-V chiplets, while the RF silicon interposer provides low-loss interconnects and hosts passive components that would otherwise consume expensive III-V die area.
Wireless systems moving into mmWave and sub-THz bands are placing heavier demands on signal handling, passive integration, and package-level design. High-speed data-centre interfaces face similar pressure as electronic and photonic interconnects are pushed toward higher bandwidths, tighter power budgets, and smaller footprints. In both cases, the dividing line between device, package, and system is becoming less distinct.
Imec’s latest work adds three elements to the interposer platform. The first is a high-density metal-insulator-metal capacitor architecture that combines a high-k aluminium-hafnium-oxide dielectric with three-dimensional oxide-stud structures in the back-end-of-line stack. The resulting MIMCAP approach is designed to provide a 10- to 100-fold increase in capacitance density compared with typical on-chip capacitors in III-V technologies.
By moving passive functions such as decoupling capacitors onto the RF silicon interposer, the platform can reduce III-V chiplet area while improving power delivery for high-frequency systems. That is a practical design shift rather than a packaging footnote, since passive content can dominate valuable die area in RF assemblies where every millimetre of compound semiconductor carries a cost penalty.
A second strand of the work is a modelling framework for RF interposer passives, validated into the sub-THz regime at around 300GHz. The framework allows circuit performance to be predicted as geometries change, reducing the need to re-simulate or measure every variation during development. Initial modelling has focused on transmission lines, with the library being extended to inductors and MIM capacitors.
The third element is laser-assisted bonding for III-V chiplet assembly on a passive-rich RF silicon interposer stack. The process has achieved alignment accuracy below 600nm and rotational misalignment below 0.05° across 43 devices, while RF measurements after assembly showed reflection below −15dB in the 110GHz to 170GHz range. Those figures point to the assembly tolerances now required when packaging becomes part of the RF circuit.
The platform builds on earlier imec work around InP chiplet integration on 300mm RF silicon interposers at 140GHz and low-loss platform performance extending to 325GHz. The new additions move the platform further into the practical engineering space, where manufacturability, repeatable assembly, validated models, and usable design libraries begin to carry as much weight as individual device performance.
The same packaging logic is emerging across other parts of the semiconductor stack. IC-Link by imec has joined TSMC’s 3DFabric Alliance, extending access to 2.5D and 3D packaging technologies for ASIC, photonics, AI, HPC, mobile, automotive, and telecom designs. In RF, the requirement is more specialised, but the direction is comparable: performance is being constructed across chiplets, interposers, passives, die-to-die links, and package assembly.
European semiconductor activity is also becoming more focused on differentiated integration rather than only on leading-edge logic density. The FAMES Pilot Line work involving CEA-Leti and GlobalFoundries is another example, with FD-SOI, embedded memory, RF, edge AI, biomedical, secure component, and 3D heterogeneous integration targets. Imec’s RF interposer platform sits in that same strategic space, where materials, packaging, and process platforms are used to build application-specific advantages.
High-frequency systems will need more than small chiplets and low-loss routing to move into production. Thermal behaviour, yield, reliability, design-rule maturity, calibration, and low-volume manufacturing support will all influence adoption. Imec’s work gives RF system developers a more complete route through those constraints by treating the interposer as an active part of the design environment, not just a substrate beneath the devices.
