IN Brief:
- IC-Link by imec has joined TSMC’s OIP 3DFabric Alliance.
- The move expands access to SoIC, CoWoS, InFO, and SoW packaging technologies.
- Advanced packaging is now central to ASIC performance, power efficiency, and manufacturing scale-up.
Imec has announced that IC-Link by imec has joined TSMC’s Open Innovation Platform 3DFabric Alliance, extending its access to advanced packaging and 3D integrated circuit technologies for ASIC and silicon photonics customers.
IC-Link, imec’s design and manufacturing service provider for ASICs and silicon photonics, will work within the 3DFabric ecosystem around TSMC-SoIC, CoWoS, InFO, and TSMC-SoW technologies. The alliance brings IC-Link closer to the foundry’s established 2.5D and 3D integration flows at a point when multi-die architectures are becoming a standard route for high-end system design.
AI, high-performance computing, mobile, automotive, and telecommunications applications are all pushing more of the design challenge into the package. Compute die, memory, RF blocks, analogue functions, high-speed interconnect, and photonic interfaces now have to be treated as parts of a single system architecture, with thermal behaviour, yield, signal integrity, and power delivery considered from the start.
IC-Link has worked with TSMC for many years, joining the Value Chain Alliance in 2009 and the Design Center Alliance in 2007. Its new role within the 3DFabric Alliance extends that relationship into one of the most active areas of semiconductor development, where scaling is increasingly achieved through package-level integration rather than through monolithic process migration alone.
Design-tool activity around TSMC has also accelerated. Siemens and TSMC have extended AI chip design work, while Synopsys and TSMC have expanded AI silicon design flows. Together, those developments show how quickly advanced-node design is becoming inseparable from packaging, verification, manufacturing, and thermal planning.
For ASIC developers, the design process now requires earlier co-optimisation between silicon, package, interposer, substrate, memory, and assembly. A multi-die approach can ease one constraint while creating another, particularly around heat dissipation, die-to-die communication, test access, and long-term manufacturing yield. Foundry-qualified packaging flows can reduce the risk of those issues appearing late in development, when redesign costs are highest.
The European dimension is also significant. Semiconductor strategy is often discussed in terms of wafer capacity, but advanced design enablement, packaging access, and manufacturable ASIC routes are just as important for companies developing AI accelerators, automotive processors, high-speed communications silicon, and silicon photonics platforms.
As transistor scaling becomes more expensive and system demands continue to rise, advanced packaging is shifting from a back-end process into the centre of design strategy. IC-Link’s entry into the 3DFabric Alliance strengthens a European route into that environment, where the package increasingly defines the performance envelope of the finished device.
