IN Brief:
- Siemens and TSMC are extending work on AI-powered semiconductor design automation.
- The collaboration spans Fuse EDA AI, Calibre, Aprisa, physical verification, advanced nodes, 3DFabric, and silicon photonics.
- AI is moving deeper into formal EDA workflows as advanced-node, chiplet, and heterogeneous designs become harder to close manually.
Siemens and TSMC have expanded their collaboration on AI-powered semiconductor design automation, with work focused on advanced-node development, design-rule closure, and physical verification.
The collaboration centres on Siemens’ Fuse EDA AI system, which automates complex, multi-step semiconductor design tasks. The companies are applying the technology to design rule check fixing, physical verification, and implementation workflows using Siemens’ Calibre and Aprisa tools alongside TSMC’s process technologies.
The work also includes certifications for Siemens EDA tools across TSMC’s latest process technologies, including 3nm, 2nm, A16, and A14 nodes. The certified flows support advanced digital, analogue, RF, and memory designs, as well as reliability-aware simulation.
The companies are extending the collaboration into 3D IC design using TSMC’s 3DFabric platform. Siemens’ Calibre tools support verification, thermal analysis, and interconnect validation for stacked chip designs. The partnership also covers silicon photonics through TSMC’s COUPE technology, bringing electrical, optical, thermal, and packaging considerations into a more closely linked design environment.
EDA automation has always carried much of the load in semiconductor scaling. At mature nodes, productivity gains often came from improved tool flows, reusable IP, and more efficient implementation. At advanced nodes, design teams face restrictive rules, power integrity constraints, variability, thermal behaviour, reliability limits, and packaging interactions that must be addressed earlier in the process.
AI-assisted EDA is now being applied to formal design tasks rather than only advisory functions. Design rule violations, physical verification cycles, and implementation bottlenecks can consume extensive engineering time, particularly when teams are working with narrow process windows. Automation can reduce iteration time when it operates inside controlled tool flows and remains compatible with sign-off requirements.
The use of Calibre and Aprisa places the AI work inside established verification and implementation environments. Physical verification remains one of the least forgiving parts of chip development, especially at advanced nodes where local layout changes can have wider effects across manufacturing rules, timing, power, and reliability. AI-driven fixes need to respect foundry decks and preserve the traceability required for final sign-off.
The 3D IC work points to the next layer of design complexity. Heterogeneous integration is becoming a practical route for improving system performance as monolithic scaling delivers smaller gains at higher cost. Stacked dies, chiplets, dense interconnects, and advanced packaging force teams to evaluate thermal paths, mechanical constraints, power delivery, and signal integrity across multiple pieces of silicon.
Silicon photonics adds another level of convergence. AI infrastructure, high-performance computing, and networking systems are driving demand for higher bandwidth and lower energy per bit, pushing optical interfaces closer to advanced semiconductor packages. Design tools therefore need to handle a broader mix of electrical, optical, and packaging data without treating each domain as a separate engineering problem.
The Siemens and TSMC collaboration places AI-driven automation within the foundry-qualified design ecosystem, where productivity gains have to sit alongside manufacturing correctness, verification discipline, and physical reliability.
