IN Brief:
- SEMI projects 300mm memory fab equipment investment will reach $52bn in 2026.
- DRAM equipment spending is expected to rise 29% to $37bn, with 3D NAND spending up 28% to $14bn.
- AI demand is reshaping memory manufacturing around HBM, DDR5, advanced-node DRAM, and higher-layer NAND.
SEMI expects worldwide 300mm fab equipment investment in the memory sector to exceed $50bn for the first time in 2026.
The industry association projects memory equipment spending will rise 29% to $52bn in 2026, before increasing by a further 11% to $57bn in 2027. The figures come from SEMI’s latest 300mm Fab Outlook and reflect continued demand for high-bandwidth memory, DDR5, AI infrastructure, data centres, and next-generation computing systems.
DRAM equipment spending is expected to grow 29% to $37bn in 2026, supported by demand for HBM and DDR5 used with GPUs and other AI accelerators. Equipment spending on 3D NAND is projected to rise 28% to $14bn, driven by increasing data-storage requirements linked to AI deployment.
SEMI also expects worldwide 300mm memory capacity to reach 4.1 million wafers per month in 2026 and 4.2 million wafers per month in 2027. Longer term, memory equipment investment is forecast to approach $80bn by 2029, supported by both capacity expansion and technology migration.
The production challenge extends beyond buying more tools. Advanced-node DRAM, HBM, and higher-layer NAND increase process complexity, add more demanding packaging requirements, and stretch yield learning across structures that are harder to manufacture than earlier generations of commodity memory. Effective capacity growth can therefore lag headline capital spending.
AI infrastructure is pulling memory back into the centre of system architecture. In the collaboration between Micron and Anthropic on AI memory bottlenecks, accelerator performance is treated as inseparable from HBM bandwidth, DRAM capacity, SSD throughput, latency, interconnect behaviour, power conversion, and cooling. SEMI’s figures provide the manufacturing-side counterpart to that demand.
HBM remains the most visible driver because it directly affects accelerator performance. Stacked DRAM, advanced packaging, and high-speed interfaces place more bandwidth close to processors, but they also create supply constraints that differ from conventional memory production. The bottleneck shifts from wafer capacity alone towards the ability to produce, stack, test, package, and qualify memory at scale.
DDR5 continues to support mainstream server and computing architectures, while 3D NAND absorbs demand from data-heavy AI workflows. Training data, checkpointing, retrieval systems, inference infrastructure, and enterprise deployment all increase storage pressure. NAND investment is therefore linked to data-centre build-out as well as conventional storage cycles.
Memory availability, cost, package choice, power consumption, and lifecycle support will be shaped by where manufacturers place capital. Designs that depend on high-performance memory have to account for qualification cycles, multi-sourcing risk, thermal design, board routing, power integrity, and controller availability.
The figures also show why memory is no longer being treated as a routine cyclical component category. AI accelerator roadmaps depend on memory bandwidth and capacity almost as much as logic performance. Constrained HBM supply can restrict accelerator shipments, while slower NAND transitions can affect storage cost and system architecture. Equipment investment is becoming an early signal for where the electronics supply chain may tighten next.
The open question is whether capital spending can translate into usable high-yield output quickly enough. AI demand has restored urgency to memory manufacturing, but the industry must still balance advanced-product shortages against the risk of overcapacity in weaker segments.
