IN Brief:
- SiTime has launched the Chorus 2 family of programmable clock generators for high-performance electronic systems.
- The devices target AI clusters, smart-factory vision systems, SmartNICs, networking, and heterogeneous compute boards.
- The family supports PCIe Gen1–Gen7 timing requirements and can replace multiple discrete clock sources.
SiTime has launched Chorus 2, a family of programmable clock generators for AI clusters, smart-factory vision systems, SmartNIC networking platforms, and heterogeneous boards combining FPGAs, ASICs, GPUs, and CPUs.
The family includes 8-output and 12-output devices in compact QFN packages. The SiT95278 provides eight outputs in a 5x5mm 40-pin QFN, while the SiT95272 provides 12 outputs in a 6x6mm 48-pin QFN. The devices are designed to replace multiple discrete oscillators or clock sources in dense digital systems.
SiTime specifies up to two times better performance, two times lower jitter, lower output skew, and improved spread-spectrum capability compared with earlier alternatives. The clock generators support PCIe timing from Gen1 to Gen7, with jitter performance below 110fs at 156.25MHz. They also provide up to 20 one-time programmable configurations and allow unused outputs to be disabled.
Clock generation becomes increasingly difficult as boards bring together high-speed serial links, accelerators, retimers, memory interfaces, networking silicon, and management controllers. Each timing domain has its own tolerance for jitter, skew, frequency accuracy, power noise, and layout-induced degradation, while board space and power budgets continue to tighten.
High-speed compute and optical interconnect development is already showing how sensitive system architecture has become to signal integrity and timing. GlobalFoundries’ SCALE optical module platform, developed for co-packaged optical interconnects in AI data-centre architectures, places photonics, high-speed signalling, packaging, and test strategy inside the same integration challenge.
AI systems are particularly demanding because bandwidth is spread across accelerators, memory, network interfaces, and storage connections. A single board may need to support PCIe, Ethernet, chip-to-chip links, management interfaces, and sensor or vision data paths. Using separate oscillators for each function can simplify early partitioning, but it increases component count, routing complexity, power consumption, and inventory burden.
Programmable clock generators reduce those constraints by consolidating timing functions while preserving configuration flexibility. A common timing device can support product variants through programming rather than hardware redesign, which is useful when boards are adapted for different accelerator options, interface speeds, or customer configurations. Disabling unused outputs can also reduce unnecessary noise and power draw.
Spread-spectrum support remains valuable as emissions limits become harder to satisfy in dense digital systems. Clock behaviour interacts with board layout, power integrity, cable routing, enclosure design, and high-speed connector performance. A programmable timing device cannot rescue a weak layout, but it can provide more useful control during compliance work and system tuning.
Lower jitter and skew also influence link reliability. PCIe Gen7 and other high-speed interfaces leave little tolerance for clock uncertainty, particularly where retimers, switches, and processors sit close together. In systems built around multiple high-current devices, maintaining clean timing across supply noise and temperature variation becomes part of the reliability challenge.
Chorus 2 arrives as timing moves from a component-selection exercise into a system-architecture decision. The more data that AI, networking, and industrial vision systems push through compact boards, the more low-jitter programmable clock distribution becomes a design constraint that has to be settled early rather than corrected late.
