Dismantled: Q2 2026

By the end of Q1, electronics design was already being pulled into a wider systems problem: faster silicon needed memory close enough to be useful, power dense enough to be deployable, packaging advanced enough to connect heterogeneous dies, and software tools capable of keeping design schedules under control. Q2 2026 did not reset that direction. It added sharper evidence that the constraints surrounding processors are now shaping architecture decisions as firmly as the processors themselves.

Among those constraints, memory provided the most visible pressure point, with Samsung Electronics moving further into HBM4E customer sampling after March’s HBM4 agreement with AMD had already shown memory planning shifting earlier into rack-scale AI architecture. HBM, DDR5, advanced-node DRAM, and higher-layer NAND are no longer separate product categories moving through a loose memory cycle; they sit inside the same capacity contest around AI infrastructure, data-centre build-out, and high-performance computing.

Those effects are distributed unevenly across the electronics market. Automotive, industrial, medical, consumer, and general embedded demand still follow different cycles, and many designs remain governed by long qualification windows, cost stability, and supplier continuity rather than top-end memory bandwidth. Even so, the investment and allocation priorities created by AI infrastructure can reach well beyond accelerator platforms, affecting equipment demand, foundry loading, substrate supply, and the practical availability of components that sit far from the headline graphics processor.

Packaging carried much the same message, although the trend predates the quarter by several years. CoWoS, SoIC, chiplets, silicon interposers, high-density substrates, and co-packaged optics were already part of the advanced semiconductor agenda before April. Q2 made their role more explicit as TSMC set out A13 process technology alongside further system-integration work around SoIC and TSMC-COUPE, while glass-core substrate development pointed to the material side of the same challenge: larger packages, finer routing, tighter dimensional control, and more difficult yield learning.

Optical interconnect developments in Q2 reinforced an ongoing shift in system architecture, where photonics is increasingly evaluated as a practical response to the scaling limits of electrical I/O in high-density, high-bandwidth environments. Photonics has been moving toward data-centre and AI infrastructure for years, and Q2 did not make co-packaged optics a universal deployment choice. It did, however, bring the technology closer to ordinary system-planning decisions in areas where electrical I/O creates power, reach, and latency penalties, with photonic AI networking work using AMD hardware showing how quickly those questions are moving from device performance toward cluster behaviour, accelerator utilisation, and deployable infrastructure.

Foundry competition now looks less like a pure node contest than it did five years ago. Process technology still sets the ceiling for density and efficiency, but PDK maturity, interface IP, packaging availability, thermal modelling, test access, and tool certification decide whether that ceiling can be reached on a realistic schedule. Samsung Foundry, TSMC, Intel Foundry, EDA suppliers, OSATs, and substrate makers are being drawn into the same practical question: how much of the surrounding ecosystem is ready when the transistor roadmap says a design can begin?

Design automation added a different form of constraint, with Cadence Design Systems giving agentic EDA workflows more specific form through its autonomous virtual engineer work and the wider industry focus on verification. AI-assisted EDA was established before Q2, but automated systems that can plan, launch, inspect, and iterate across multi-step workflows change the burden placed on constraints, traceability, and sign-off. In chip design, confidence without auditability is a liability.

Embedded electronics followed the same pattern at a different scale, as Texas Instruments and other MCU suppliers pushed AI acceleration further into lower-power devices while virtual evaluation environments shortened the gap between silicon selection and software development. TinyML and edge inference have been familiar for years, but integrated MCU NPUs, cloud-based virtual evaluation, and RISC-V access before hardware availability are changing how early design work is sequenced. Memory footprint, sensor quality, interrupt behaviour, latency, functional safety, cybersecurity, and software maintenance all determine whether local inference survives contact with a real product.

Power delivery emerged as one of the quarter’s more understated yet fundamentally physical design challenges, reflecting constraints that are less visible in headline specifications but critical to system viability. The move toward higher-voltage DC distribution in AI infrastructure was already visible before Q2, but the arrival of more 800VDC auxiliary supplies from Power Integrations, GaN and SiC conversion platforms, and rack-level power demonstrations showed how quickly that discussion is spreading from facility architecture into board-level design. AI infrastructure remains limited by electricity, heat, copper, protection, and serviceability long before accelerator branding runs out.

Across the quarter, the defining pattern was less about the arrival of entirely new ideas and more about the steady layering of existing developments into a more complex whole. Memory roadmaps, packaging capacity, optical links, autonomous verification, embedded AI tools, power conversion, and export-control exposure are all becoming harder to separate from the core electronics design brief. The next stage of competition will be less about whether a company can produce an impressive component in isolation, and more about whether that component can be manufactured, powered, cooled, verified, qualified, and supplied inside a system that has to work at scale.

What were Q2 2026’s biggest electronics design stories?

Samsung pushes HBM4E into customer sampling

When Samsung Electronics began shipping 12-layer HBM4E samples to major customers in Q2, the immediate development was a product milestone rather than a new market direction. HBM had already become central to AI accelerator planning, and Samsung’s March HBM4 alignment with AMD had already placed memory supply inside the architecture of future rack-scale systems. The quarter’s new detail was the move from roadmap alignment to customer sampling for a faster, higher-bandwidth HBM4E device.

The 12-layer sample provides 48GB of capacity and uses Samsung’s sixth-generation 10nm-class 1c DRAM with a 4nm logic base die. The device is designed for up to 14Gbps per pin, with scalability to 16Gbps, and Samsung has indicated that 32GB and 64GB configurations will follow across 8-layer, 12-layer, and 16-layer stacks. On paper, those figures belong to memory products; in practice, they belong to whole AI platforms.

The sampling followed the Samsung-AMD HBM4 agreement around future Instinct accelerators, where bandwidth, power, packaging, and platform integration were already being treated as connected design variables. That earlier agreement helps keep the chronology accurate. HBM was not suddenly discovered in May, and the quarter did not convert memory from a procurement line into a design constraint for the first time. It advanced the qualification process for a next-generation part that sits inside a trend already running through accelerator, CPU, rack, and memory roadmaps.

Memory capital spending gives the product milestone a manufacturing counterpart. SEMI’s 300mm memory equipment projection put 2026 investment above $50bn, with DRAM and 3D NAND both rising as AI infrastructure demand feeds into HBM, DDR5, advanced-node DRAM, and higher-layer NAND. Tool spending, however, is not the same thing as usable supply. Advanced memory capacity depends on process stability, yield, materials, lithography availability, stacking capability, testing, and the pace at which customers can qualify devices inside their own platforms.

Within AI accelerators, memory now governs more than data movement. A compute die that cannot be fed efficiently becomes an expensive thermal object, and the surrounding package must support bandwidth, power, routing density, and heat flow at the same time. HBM therefore belongs near the beginning of architecture work, not near the end of procurement. Interposer design, substrate availability, power distribution, and mechanical limits all become part of the memory decision.

That high-end pressure can still affect markets that will never use HBM. Equipment allocation, advanced DRAM investment, supplier attention, and pricing behaviour can shift when the largest customers reserve capacity around AI infrastructure. Industrial, automotive, and embedded products tend to have longer lifecycles and less tolerance for volatile component strategy, so the spread of AI-led memory investment into the wider supply chain needs careful handling rather than easy optimism.

Customer sampling also leaves several commercial questions unresolved. Qualification for large AI customers can run through demanding thermal, reliability, signal-integrity, and platform-level tests, while the competitive field around SK hynix, Micron, and Samsung remains tied to yield, package integration, and customer-specific schedules. A technically strong HBM stack still has to become a dependable supply item in systems where delays can cascade into accelerator availability, rack integration, and data-centre deployment planning.

Samsung’s Q2 memory development was practical rather than symbolic. HBM4E moved into customer sampling, manufacturing investment continued to rise, and AI platforms remained constrained by the relationship between compute and bandwidth. The underlying direction was already visible before April; Q2 gave it harder numbers and closer qualification work.

TSMC extends scaling into packaging and optics

At its 2026 technology symposium, TSMC introduced A13 process technology while giving substantial space to SoIC, CoWoS, and co-packaged optics. The headline node update was only part of the quarter’s development. A13 extends the A14 family through an optical shrink, while A14-to-A14 SoIC is scheduled for production availability in 2029 and is designed to raise die-to-die I/O density compared with N2-on-N2 SoIC.

The more immediate Q2 marker came from TSMC-COUPE, the company’s Compact Universal Photonic Engine. TSMC set out a co-packaged optics route using COUPE on substrate, with production beginning in 2026 and stated gains in power efficiency and latency against a pluggable optical implementation on the circuit board. Co-packaged optics has been discussed for years, so the quarter should not be treated as its starting point. The change lies in its place on a foundry integration roadmap beside leading-edge process and 3D stacking.

Advanced packaging has followed a similar path. CoWoS, silicon interposers, chiplets, and 3D integration were already central to AI and high-performance computing before April. Q2 gave those technologies a more integrated role in the same discussion as process scaling. A faster or denser transistor platform cannot deliver full system value if the package cannot connect compute dies, memory stacks, and optical engines efficiently enough, or if assembly capacity remains the limiting step.

The trajectory of substrate development illustrates how rapidly system-level pressures are propagating into the materials layer, reshaping requirements at a fundamental level. Work on glass-core substrates for AI packaging has been driven by the need for larger package formats, finer interconnects, and tighter dimensional stability. These materials are not ready for broad adoption, and limited-volume production is still expected to develop gradually as process control, standards, equipment, and qualification mature. Their inclusion in AI, HPC, co-packaged optics, and advanced processor roadmaps still shows how far packaging constraints have moved upstream.

Optics adds another set of trade-offs. Electrical I/O continues to serve most systems effectively, and pluggable optics will not vanish because a co-packaged route becomes available. Bringing optical engines closer to compute can reduce power per bit and latency, but it also introduces thermal coupling, serviceability questions, optical alignment issues, test complexity, and yield exposure at the package level. The decision becomes architectural rather than cosmetic.

The same direction was visible immediately after the quarter in photonic AI networking work using AMD hardware, where the question moved beyond a photonic component and into cluster throughput, latency, and accelerator utilisation. Although that deployment sits just outside the Q2 window, it reflects the same pressure that TSMC’s roadmap addresses: AI infrastructure increasingly depends on how data moves through packages, boards, racks, and networks.

Foundry selection now carries more dependencies than a process-node comparison can capture. PDK maturity, EDA certification, IP availability, package route, thermal model, substrate access, test coverage, and volume assembly capacity all sit close to the design schedule. A leading process can be commercially awkward if the surrounding route is immature, while an older or less aggressive process can be more attractive if the ecosystem reduces qualification risk.

TSMC’s Q2 roadmap reinforced a continuing shift from transistor-centred scaling toward system-centred scaling. The company did not make packaging or optics important for the first time; it placed them more tightly inside the roadmap that determines how advanced silicon becomes deployable hardware. The result is a more demanding design front end, where process, package, memory, optics, and test have to be considered together.

Cadence brings agentic EDA into verification

When Cadence Design Systems introduced its autonomous virtual engineer for chip design at Computex 2026, the development landed in a market already accustomed to AI-assisted EDA. Machine learning has been used for layout optimisation, design-space exploration, regression support, and tool productivity for years. Q2 added a more assertive form of workflow automation, with an agentic system designed to plan and execute more complex semiconductor development tasks across multiple steps.

The distinction between AI assistance and agentic execution is important without being mystical, because it reflects a shift in how responsibility is distributed across the design process rather than a sudden change in capability. A tool that suggests options or optimises a narrow problem still leaves orchestration largely with the engineer, who remains responsible for sequencing tasks, interpreting results, and deciding how individual outputs fit into the wider design context. An agentic workflow can launch simulations, inspect failures, adjust parameters, triage logs, co-ordinate tasks, and iterate against defined objectives. That increases the value of well-formed constraints, clean data, and disciplined review, because an automated system can scale both useful work and avoidable error.

Verification is the most immediate pressure point, as it must reconcile growing system complexity with the need for reliable sign-off. Large SoCs, multi-die packages, and AI accelerators already generate vast simulation, regression, debug, and coverage workloads. As designs absorb more power, thermal, electromagnetic, photonic, and package-level interactions, the verification problem becomes less about running one more test and more about deciding which evidence is sufficient for sign-off. Synopsys’ June work around integrated multiphysics closure sits in the same industrial context: design closure is spreading across domains that were previously handled with cleaner boundaries.

Cadence’s Q2 announcement also came during a period in which chip design software demand was being pulled upward by AI infrastructure, hyperscaler silicon, custom accelerators, and more complicated packaging strategies. The value of EDA automation lies as much in schedule control as in headline productivity. Faster simulation orchestration, better regression triage, and earlier detection of cross-domain problems can change the economics of a design cycle, especially where teams are being asked to support more variants, tighter tape-out windows, and more aggressive power targets.

Hardware remains unforgiving. A design agent that produces a plausible answer still has to operate inside sign-off discipline, tool qualification, auditability, and company-specific design rules. A software bug can often be patched after release; a silicon error can become a respin, a cancelled customer commitment, or a delayed platform. Autonomous execution therefore needs traceable decisions, controlled permissions, versioned constraints, and human authority at the points where risk moves from exploration to commitment.

The packaging direction seen elsewhere in Q2 increases that burden. When chiplets, HBM, optical engines, and advanced substrates are combined in one system, a change in one domain can alter another. A layout adjustment can affect thermal behaviour; a package choice can affect signal integrity and test access; power delivery can change timing margin; photonic integration can create thermal-optical sensitivities. Automation can help navigate that design space, but only if the toolchain understands the links well enough to avoid local optimisation at system expense.

The adoption curve will probably be uneven. Large semiconductor companies and hyperscalers have internal design history, compute infrastructure, proprietary verification environments, and the budget to integrate agentic workflows into controlled engineering processes. Smaller design teams may benefit through commercial EDA platforms, but they will still need governance, repeatability, and careful boundary-setting. The risk is not that engineers disappear; it is that automation is treated as a substitute for engineering judgement in flows where judgement is still the final safety mechanism.

Cadence’s agentic EDA work made autonomous workflow ambitions more concrete, particularly around verification and design orchestration, while leaving the hardest question unchanged: how much of a chip design process can be automated without weakening the evidence needed to trust the final device?

Edge AI moves further down the embedded stack

The spread of edge AI in Q2 2026 continued a trend that had been building through TinyML, industrial sensing, automotive perception, and local signal processing for several years. Texas Instruments had already set an important pre-quarter marker by adding TinyEngine NPU acceleration to new MCU families, bringing dedicated inference hardware into devices that would previously have relied on a general-purpose CPU or a larger application processor.

That March launch keeps the chronology grounded. Local inference was already established in vision, vibration analysis, predictive maintenance, voice, gesture, and low-power sensing. The continuing shift is architectural: acceleration is spreading into smaller, cheaper, and lower-power controllers, while software evaluation and model deployment are being pulled earlier into the design cycle.

Texas Instruments’ TinyEngine figures show why that movement has technical force. The company specifies up to 90 times lower latency and more than 120 times lower energy per inference compared with similar MCUs without an accelerator, although those figures depend on workload and implementation. A dedicated block can move inference into power and latency budgets that are difficult to meet through CPU execution alone. That changes the feasibility of battery-powered sensing, compact industrial controls, and distributed intelligence at the edge.

Infineon Technologies added a different Q2 signal through its AWS-powered virtual platform for automotive MCU evaluation. The platform supports browser-based workflows, hundreds of concurrent users, Quick Mode testing, Expert Mode development, and early access to next-generation RISC-V architecture before physical hardware would usually be available. The design issue is not restricted to automotive, even though software-defined vehicles make the pressure especially visible.

As embedded devices take on more software, more connectivity, and more safety-related functions, early evaluation can no longer wait comfortably for boards, debuggers, and local toolchain configuration. Virtual platforms do not replace hardware validation, EMC testing, timing analysis, thermal checks, or functional safety assessment. They do allow architecture comparison, application prototyping, and software familiarisation to begin earlier, reducing idle time between silicon selection and meaningful development.

The proposed onsemi-Synaptics transaction added a consolidation signal at the end of the quarter. onsemi agreed to acquire Synaptics in an all-stock deal valued at approximately $7bn, bringing together power, sensing, edge AI compute, wireless connectivity, human-machine interface technology, and control. The transaction remains subject to shareholder and regulatory approvals, with completion expected in mid-2027, so it should not be treated as an already integrated platform.

Its direction is still instructive. Edge AI products rarely depend on compute alone. They need sensors that generate usable data, power stages that support the duty cycle, memory that fits the model and firmware, connectivity that does not compromise security, and software that can be maintained across long deployments. Suppliers are trying to reduce integration friction by combining more of that design surface into reference platforms, software stacks, and product portfolios.

That approach can simplify development, but it can also increase supplier dependency. A more integrated platform may reduce interface risk and shorten early design work, while making long-term sourcing, migration, security updates, and second-source planning more complicated. The trade-off is familiar in embedded electronics, where product lifecycles often outlast fashionable architectures and where certification, support, and availability are as important as benchmark performance.

Q2 continued the movement of AI into embedded systems without turning every MCU into a neural-computing platform. Dedicated NPUs, virtual evaluation environments, and supplier consolidation all point in the same direction: local inference is becoming one design variable among many. Memory footprint, interrupt behaviour, sensor placement, real-time control, cybersecurity, functional safety, update strategy, and power budget remain the conditions that decide whether edge AI becomes a reliable product function.

AI infrastructure pulls power electronics upstream

Power Integrations introduced compact 800VDC auxiliary power supply reference designs in June for NVIDIA Kyber AI data-centre architectures, using 1700V PowiGaN InnoMux-2 ICs. The designs are modest in output power, at 15W and 35W, but they belong to a much larger movement in data-centre electrical architecture. Higher rack power is forcing conversion, isolation, monitoring, and protection decisions closer to the beginning of system design.

The 800VDC direction was not new in Q2. The move toward higher-voltage distribution in AI data centres had already been discussed as a route to reducing current, copper, conversion losses, and thermal stress at rack scale. The quarter added more product-level evidence, including Power Integrations’ auxiliary PSU designs and Navitas power demonstrations at PCIM, both addressing pieces of the same conversion chain.

Auxiliary power can look peripheral beside high-wattage converter platforms, yet the control electronics around an 800VDC architecture still require dependable isolated low-voltage rails. Gate drivers, sensing circuits, supervisory controllers, communications, protection functions, and monitoring devices all sit behind those rails. If a small supply fails or behaves poorly under transients, the wider rack can inherit the problem through protection errors, control instability, or loss of telemetry.

Navitas Semiconductor used PCIM Europe 2026 to show GaN and SiC technologies for AI data centres, grid infrastructure, and industrial electrification. Its AI data-centre line-up included an 800V-to-6V GaN-based power delivery board targeting 97.5% peak efficiency and an 800V-to-50V full-brick converter platform targeting 98.5% peak efficiency. Those designs point toward fewer conversion stages, denser power delivery, and a more active role for wide-bandgap devices where switching speed, voltage capability, and thermal behaviour can be used effectively.

NVIDIA supplied the demand-side scale in May, reporting first-quarter fiscal 2027 revenue of $81.6bn and data-centre revenue of $75.2bn. Those figures do not make every AI infrastructure design sensible, nor do they remove the economics of energy cost, grid connection, and cooling. They do explain why power suppliers are aligning products around AI racks, where deployed compute depends on electrical and thermal systems as much as accelerator availability.

Higher-voltage DC distribution can reduce current for a given power level, but it also raises the standard for insulation, protection, fault handling, creepage, clearance, maintenance procedures, and test coverage. GaN and SiC devices can improve efficiency and density in suitable stages, but neither material removes the need for disciplined layout, gate-drive control, EMI management, thermal modelling, and reliability qualification. A stage-specific advantage can disappear quickly if packaging, parasitics, or cooling are mishandled.

The power discussion also links back to packaging and memory. Higher accelerator density increases current demand at the board and package level, while HBM and chiplet integration add their own power-integrity and thermal constraints. As rack architectures move toward higher voltage and denser conversion, the boundary between facility power, rack power, board power, and silicon power becomes less forgiving. Losses that were tolerable at lower density become expensive, hot, and difficult to service.

Q2’s power electronics activity showed continuation with greater practical definition. Reference designs, demonstrators, and power-device roadmaps are converging around the same physical limit: AI infrastructure cannot scale on compute silicon alone. The second half of 2026 will test how much of the 800VDC and wide-bandgap discussion moves from demonstrations into qualified deployments, where long-duration reliability, safety, field maintenance, and manufacturability will matter as much as peak efficiency.

IN answer to…

Four questions shaping the quarter’s electronics design agenda.

Why did memory dominate electronics design discussion in Q2 2026?

Memory sat at the centre of Q2 because AI infrastructure demand continued to link HBM, DDR5, advanced-node DRAM, and higher-layer NAND to system performance, supply allocation, and capital spending. Samsung’s HBM4E sampling and SEMI’s 300mm memory equipment projection both showed the same pressure from different ends of the supply chain: accelerator architectures need more bandwidth, and manufacturing capacity has to catch up through expensive, technically demanding investment.

Did advanced packaging become important only during Q2 2026?

No. Advanced packaging had already become central to AI accelerators, chiplets, and high-performance computing. Q2 made the dependency more explicit through TSMC’s A13, SoIC, and TSMC-COUPE roadmap, alongside continuing substrate work around larger packages, finer routing, and tighter dimensional control. The quarter advanced an existing trend rather than starting one.

Will agentic AI replace chip design engineers?

Agentic AI is more likely to reshape verification, simulation orchestration, regression management, and design-space exploration than remove engineering responsibility. Chip design still requires constraints, traceability, sign-off discipline, and review because hardware errors can lead to respins, qualification delays, and missed customer schedules. The useful productivity gains sit inside controlled workflows, not outside them.

What changed for embedded and edge AI during Q2 2026?

Edge AI continued moving into lower-power embedded platforms while software evaluation shifted earlier in the design cycle. MCU NPUs, virtual automotive MCU evaluation, RISC-V access before hardware availability, and edge-AI consolidation all pointed toward the same direction. Local inference is becoming a normal embedded design variable, alongside power, memory, latency, safety, security, and lifecycle support.