MIPS pushes RISC-V for physical AI

MIPS is advancing its physical AI strategy around RISC-V compute subsystems for autonomous edge platforms that need to sense, think, act, and communicate in real time.

The company is applying its Atlas portfolio to workloads in automotive, aerospace, industrial automation, robotics, communications infrastructure, enterprise storage, and embedded systems. The platform approach treats physical AI as a closed-loop compute problem, where perception and decision-making are tied to real-world movement, safety, and timing.

Machines operating in physical environments require different processor characteristics from cloud AI systems. A robot, vehicle, drone, or industrial platform must interpret sensors, make decisions, and control motion under strict latency and reliability constraints. Deterministic behaviour, safety support, failure handling, and software control sit beside AI throughput as core processor requirements.

MIPS breaks the physical AI problem into sense, think, act, and communicate functions. Its Atlas portfolio includes processors and subsystems for ADAS sensing, AI acceleration, real-time microcontroller functions, and robotics. Customer references include Mobileye using the Atlas P8700 safety-certified RISC-V processor for ADAS, ForwardEdge ASIC selecting the S8200 NPU for aerospace, and Inova Semi selecting the M8500 real-time RISC-V microcontroller for robotics.

The same design pressure is visible in distribution and deployment. Rutronik’s addition of Intel processors for physical AI pointed to industrial systems that need local compute for machine perception, automation, and responsive control. MIPS approaches the same shift from processor IP and compute-subsystem architecture.

RISC-V adds strategic flexibility to the processor discussion. The open instruction-set architecture is moving into production planning across automotive, industrial, embedded, and safety-related markets, where tailored implementations can support workload-specific acceleration and system-level optimisation. In physical AI, that flexibility can help partition compute between real-time control, AI acceleration, safety monitoring, and communication functions.

The ecosystem remains the harder test. Safety-related and long-lifecycle platforms need compilers, debuggers, operating systems, middleware, simulation, trace, verification, and certification routes that remain stable through development and production. A processor core can deliver strong technical attributes, but adoption depends on the surrounding software and validation environment.

Those validation routes become especially important when AI acceleration shares silicon resources with real-time control. Toolchains must expose enough timing, trace, and diagnostic behaviour for integrators to prove that perception workloads do not compromise safety-critical response paths.

Physical AI also ties processor design more closely to sensors. Cameras, radar, lidar, inertial measurement units, position sensors, microphones, and industrial transducers produce data that must be fused and acted upon quickly. Sensor-interface standardisation around MIPI and industrial edge AI platforms from Advantech reflect the same convergence between sensing, compute, and local decision-making.

The design burden extends beyond normal operation. Physical AI systems must handle degraded sensors, thermal throttling, communication loss, firmware updates, cybersecurity events, actuator faults, and unpredictable environments. Compute platforms therefore need isolation, monitoring, real-time response, and safe fallback modes, not only neural-network acceleration.

Automotive and aerospace applications raise the requirements further because processor behaviour can influence vehicle control, mission execution, and autonomous movement. Industrial robotics brings similar demands where machines operate close to people, heavy payloads, or production assets. In these environments, timing confidence and failure behaviour are as important as benchmark performance.

MIPS’ focus on RISC-V for physical AI reflects a shift from AI that classifies data to AI that acts on the physical world. Once an algorithm controls motion, force, or safety-critical behaviour, the processor architecture must support predictable execution as well as efficient inference. Physical AI will be shaped by platforms that combine performance with deterministic control, mature tooling, and credible safety pathways.