IN Brief:
- Rhea1 first silicon has run Linux, high-bandwidth memory, and established high-performance computing benchmarks.
- Demonstrations combined Arm hosts, RISC-V acceleration, scientific software, European design tools, and memory compression.
- Follow-on programmes must convert working prototypes into repeatable processor supply, supported systems, and deployable software.
The European Processor Initiative has completed the second stage of its processor and accelerator programme after demonstrating working Rhea1 silicon, RISC-V acceleration, scientific software, European electronic-design-automation tools, and memory-compression technology.
During the final programme review in Luxembourg, first silicon of the Rhea1 processor ran a complete high-performance computing software stack on a test board. The system booted a standard Linux distribution, operated with high-bandwidth memory, and executed HPL and STREAM benchmarks used to assess computational throughput and memory performance.
Developed by SiPearl, Rhea1 contains 80 Arm Neoverse V1 cores and 61 billion transistors. Its architecture is intended for exascale computing, artificial intelligence, engineering simulation, scientific research, and security-sensitive data-centre workloads in which processor access and supply-chain control have acquired strategic weight.
Five accelerator demonstrations accompanied the processor work, including a vector-computing design based on RISC-V technology. A scientific atmospheric-diffusion application ran across a multi-FPGA cluster using OpenMP, MPI, an LLVM-derived toolchain, and established performance-analysis tools, connecting the accelerator architecture with a recognisable software environment rather than an isolated instruction-set demonstration.
Another system linked an EPAC 1.5 RISC-V test chip to an Arm host through PCI Express, with code for both instruction-set architectures combined within one executable. RISC-V sections were transferred to the accelerator using direct memory access before execution and return of the resulting data.
Additional work covered Kalray’s KVX architecture, Menta’s Origami design software, and ZeroPoint’s DenseMem memory-compression technology. Together, the projects addressed processor silicon, specialised acceleration, toolchains, design implementation, and the widening gap between processor throughput and effective memory bandwidth.
Working silicon shifts attention towards deployment
Completing a funded development stage does not create a self-sustaining processor industry, although it establishes a firmer technical base from which one can be built. The initiative has produced complex silicon, accelerator intellectual property, compilers, software tools, and application demonstrations; each element must now be qualified, manufactured, integrated, supported, and updated over the working life of an operational computing system.
Rhea1’s successful boot and benchmark execution show that memory controllers, firmware, packaging, clocking, power delivery, and operating-system support have functioned together on first silicon. Simulation and emulation can expose many design defects before fabrication, but complete hardware frequently reveals interactions involving signal integrity, power sequencing, thermal behaviour, and device timing that are difficult to reproduce fully before manufacture.
European processor policy is increasingly connected with the continent’s wider semiconductor materials, equipment, packaging, and test capability. Germany has allocated support to four projects spanning silicon carbide, MOSFETs, metrology, and detector technology, while Thales has established a European advanced-packaging operation through Tessalia. Processor sovereignty remains dependent on substrates, memory, packaging, board manufacture, cooling, and test systems distributed across several supply chains.
The mixture of Arm and RISC-V technology reflects a practical division of strengths. Arm supplies a mature server ecosystem and established software base, whereas RISC-V provides greater latitude for specialised accelerators and locally controlled architectural extensions. Heterogeneous execution nevertheless creates additional compiler, debugger, scheduling, and memory-coherency work, and applications must gain enough performance to justify moving data across interfaces.
Electronic-design-automation capability represents another strategic dependency because advanced devices cannot be produced without tools capable of placing, routing, verifying, and signing off enormous designs within workable schedules. Menta’s reported acceleration of placement tasks addresses one stage of that flow, while physical verification, timing closure, power integrity, formal checking, and manufacturing sign-off remain equally important.
Memory compression addresses a different bottleneck. As processor and accelerator throughput rises, performance is increasingly limited by the energy and time required to move data rather than execute arithmetic. Hardware compression can increase effective memory capacity and bandwidth, although its gains depend on data characteristics, latency, implementation overhead, and software transparency.
Follow-on programmes including EUPEX, EUPILOT, and DARE inherit the task of turning demonstrators into systems that can be programmed and operated without detailed knowledge of every hardware layer. Consistent software environments, maintained toolchains, reference platforms, documentation, and support will determine whether the resulting technology moves beyond a sequence of research projects.
The initiative now has working silicon and a substantial collection of surrounding technologies. Repeatable manufacture, installation in operational machines, and the delivery of successive processor generations will determine whether those results develop into durable European computing capacity.
