IN Brief:
- A mobile ancillary spin travelled along a silicon shuttling bus to interact with four stationary data qubits.
- The five-qubit processor executed X- and Z-type parity checks up to weight four and generated multi-qubit entanglement.
- The sparse architecture could reduce fixed coupling, wiring congestion, and readout constraints in larger silicon quantum processors.
QuTech researchers and collaborators have demonstrated a five-qubit silicon processor in which one mobile electron spin travels along a shuttling bus to interact with four stationary data qubits. The device completed X- and Z-type parity checks up to weight four, a core operation in surface-code quantum error correction.
The processor is built in an isotopically purified silicon-28/silicon-germanium heterostructure. Its gate layout defines a readout zone, a transport channel, and four isolated quantum-dot locations described by the researchers as bus stops. A mobile ancillary qubit moves between those stops, allowing each stationary spin to interact with the same controllable quantum carrier.
Semiconductor spin-qubit layouts usually depend on interactions between neighbouring devices. Extending that approach across a large array requires information to pass through intermediate qubits or demands a dense network of couplers, control lines, and readout structures, increasing chip area, calibration effort, and the risk of electrical crosstalk.
The shuttling architecture replaces part of that fixed connectivity with controlled physical motion. A four-phase travelling-wave potential transports the electron along the bus, while an on-chip cobalt micromagnet establishes the magnetic-field profile used to control the spins. The experiment operated without an external magnetic field after the micromagnet had been magnetised, and the transport speed was approximately 1.8m/s.
During processor operation, the mobile spin completed a 1.2µm round trip with an identity-operation fidelity of 97.7%. It was repeatedly positioned beside the four data qubits so that exchange interactions could implement two-qubit operations. The researchers also developed remote-tuning procedures because conventional charge sensing was available only near one end of the array.
Remote calibration is central to the design. Sparse layouts become useful only when distant quantum dots can be populated, tuned, controlled, and measured without placing a charge sensor beside every device. The team used the phase accumulated by the transported spin to identify charge transitions and calibrate the electrostatic conditions at each bus stop.
The resulting control stack supported universal operation of the effective five-qubit processor. A quantum non-demolition measurement scheme initialised and read the mobile ancilla and four data qubits, while coherent shuttling, electric-dipole spin resonance, and exchange-based gates provided the required single- and two-qubit operations.
The most consequential demonstration was a weight-four parity check. Surface-code error correction requires an ancillary qubit to interact with four data qubits and report their combined parity without destroying the encoded information. In the QuTech device, the mobile spin visited the four bus stops sequentially, collecting the information required for the check rather than relying on permanent couplings across a tightly packed array.
The shortest weight-four parity-check circuit took 4.84µs. The same connectivity generated multi-qubit entanglement, including genuine five-qubit Greenberger–Horne–Zeilinger states, showing that the shuttling bus can support calibrated processor operations rather than merely transporting an isolated spin.
The device remains experimental, and the reported error budget identifies two-qubit interactions rather than transport as the dominant limitation during five-qubit operation. Shuttling fidelity, exchange noise, device uniformity, and automated calibration will all need to improve before the architecture can be repeated across much larger arrays.
Sparse layouts address a physical problem that becomes harder as qubit counts rise. Readout resonators, reservoirs, radio-frequency lines, and control electrodes are considerably larger than the spins they manipulate, so placing every qubit close to every required interface is unlikely to scale cleanly. Moving a coherent spin between functional zones creates room for those supporting structures and allows connectivity to be reconfigured through control sequences.
The experiment shifts part of quantum-processor scaling from static interconnect design into transport and calibration engineering. Larger systems will still require higher-fidelity gates, repeatable fabrication, cryogenic control, and fault-tolerant protocols, but the five-qubit processor shows that mobile spins can serve as working interconnects between silicon registers.
