IN Brief:
- A Switchtec PCIe 6 fanout switch connects host processors to multiple Micron 9650 NVMe SSDs.
- PCIe 6.0 provides 64GT/s per lane, while the 3nm switch adds diagnostics, error containment, multicast, and security.
- Production performance will depend on topology, software, thermals, lane allocation, and oversubscription.
Microchip Technology and Micron have demonstrated an end-to-end PCIe 6.0 storage architecture connecting host processors to multiple Micron 9650 NVMe solid-state drives through a Switchtec Gen 6 fanout switch. The system is being shown at the 2026 Future of Memory and Storage conference in California.
PCIe 6.0 doubles the per-lane transfer rate of PCIe 5.0 to 64GT/s, increasing the available bandwidth between processors, accelerators, switches, and storage devices. In the demonstration, the Switchtec device provides the central interconnect, allowing several Gen 6 SSDs to operate behind one switching fabric rather than through isolated point-to-point links.
The arrangement is aimed at composable and disaggregated infrastructure, where storage can be allocated across systems instead of being fixed permanently to one server. A fanout switch expands the number of devices accessible from a host and supports more flexible topologies, although predictable latency and sufficient upstream bandwidth are needed to prevent congestion simply moving into the switch.
Microchip’s Switchtec Gen 6 family is manufactured on a 3nm process and supports high lane counts, error containment, diagnostics, and multicast. The multicast function can distribute the same data to several endpoints within a PCIe domain, reducing repeated host transfers when multiple accelerators or storage devices require a common data set.
The switches also incorporate secure boot and a hardware root of trust. Microchip says the cryptographic architecture includes post-quantum-safe algorithms aligned with CNSA 2.0 requirements, placing interconnect silicon inside the platform security boundary rather than treating it as a transparent board component.
Brian McCarson, corporate vice-president and general manager of Microchip’s data centre solutions business unit, said: “Advancing data center performance is not solved by any single component and our work with Micron highlights the importance of taking a cohesive approach.” The demonstration is consequently more useful as a compatibility and topology exercise than as a claim about one component’s peak figure.
Micron’s 9650 is a production PCIe Gen 6 data centre SSD with sequential read performance of up to 28GB/s and more than 5.5 million input-output operations per second, depending on configuration and workload. Micron also states that the drive can provide twice the performance of a Gen 5 device at the same 25W power state.
Connecting several drives at those rates creates an aggregate bandwidth requirement that can exceed the links available from a single processor socket. Switch configuration, lane allocation, oversubscription, and traffic arbitration therefore become central design decisions. A fabric tuned for large sequential transfers may behave differently under small random reads or mixed workloads shared by several accelerators.
AI infrastructure adds another constraint because storage performance does not translate directly into accelerator utilisation. Training and inference pipelines move data through storage, host memory, network interfaces, accelerator memory, and software frameworks, and the slowest stage can dominate the result even when the SSD and switch each meet their individual specifications.
The demonstration does not disclose a complete benchmark, exact topology, lane allocation, or measured end-to-end latency. It proves that the components can be combined at Gen 6 speed, but does not establish how a particular server or rack design will perform under production workloads.
For data centre designers, the practical value lies in having switching and storage devices available within the same interface generation. Early systems would otherwise mix Gen 6 endpoints with older switches or bridges, sacrificing bandwidth and complicating validation. A matched fabric also gives firmware and operating-system teams a more realistic environment for testing error recovery, hot-plug behaviour, telemetry, and security controls.
PCIe 6.0 storage is moving beyond individual controller and drive announcements into complete architectures. Power delivery, signal integrity, cooling, cabling, software orchestration, and failure isolation will decide whether the additional bandwidth produces useful throughput or merely reaches the next bottleneck faster.
