IN Brief:
- A 28nm bit-parallel SRAM compute-in-memory macro targets multi-bit edge-AI workloads.
- Its architecture addresses signed computation, routing congestion, and redundant internal switching.
- Reported peak efficiency reaches 106.85TOPS/W for INT8 and 77.68TFLOPS/W for BF16 operation.
Researchers at Xidian University have demonstrated a 28nm bit-parallel SRAM compute-in-memory macro designed to reduce data movement while supporting multi-bit INT8 and BF16 arithmetic for edge-AI processing.
Compute-in-memory moves arithmetic into or closer to the memory array, reducing the repeated transfer of weights and intermediate data between separate storage and processing blocks. That approach can cut one of the major energy costs in machine-learning hardware, although integrating useful multi-bit computation inside SRAM introduces additional circuit overhead of its own.
The new macro focuses on three of those overheads: signed arithmetic, routing congestion, and unnecessary switching inside the accumulation path. These problems become increasingly important as compute-in-memory designs move beyond binary demonstrations towards numerical formats that can support practical neural-network inference.
The architecture uses a sign-bit-embedded approach with transition-counting lines and stage-wise-enabled accumulation. Incorporating sign handling into the compute structure is intended to reduce the additional circuitry normally required to process positive and negative values, while staged activation prevents parts of the accumulation chain from switching when their contribution is not required.
That switching activity matters because the energy cost of an arithmetic operation is not confined to the multiplier or accumulator. Internal wires, logic nodes, bit lines, and intermediate storage all consume energy when their capacitances are charged and discharged. A design can therefore reduce external memory traffic and still lose much of that advantage through unnecessary activity inside the compute array.
Bit-parallel operation creates a related routing challenge. Processing several bits simultaneously can increase throughput and avoid long serial-computation sequences, but it requires more local signals and more complex accumulation. As array dimensions and precision increase, moving those intermediate values around the macro can consume both silicon area and power.
The sign-bit-embedded architecture is intended to handle signed arithmetic without adding a large separate correction network. Stage-wise activation then reduces redundant switching by enabling only the portions of the computation required at a particular point in the operation.
The fabricated 28nm implementation supports both INT8 and BF16 multiply-accumulate processing. Peak energy efficiency is reported at 106.85TOPS/W for INT8 operation and 77.68TFLOPS/W for BF16. Those results characterise the macro itself rather than a complete processor containing control logic, external interfaces, larger memory hierarchies, and application software.
Support for BF16 is significant because edge-AI accelerators do not always operate comfortably with fixed integer precision. INT8 remains attractive where neural networks can be quantised aggressively without unacceptable accuracy loss, but a floating-point-derived format such as BF16 provides a wider dynamic range for models or processing stages that are less tolerant of fixed-point arithmetic.
Supporting both formats within a compute-in-memory architecture increases flexibility, although it also increases circuit complexity. The design challenge is to provide that numerical range without allowing conversion, accumulation, and routing circuitry to consume the energy saved by keeping data inside the memory array.
SRAM also brings its own trade-offs. It integrates readily with established CMOS logic and provides fast read and write performance, but conventional SRAM bit cells occupy more silicon area than many emerging non-volatile memories. That puts additional pressure on designers to make the compute circuitry around the array efficient enough to justify the area cost.
Commercial edge-AI processors require considerably more than a successful memory macro. Scheduling, activation functions, data movement outside the array, interfaces, software tools, and workload mapping all affect system efficiency, while process variation and thermal behaviour influence repeatability in manufactured silicon.
The 28nm result is therefore an architectural demonstration rather than a finished accelerator. Its relevance lies in tackling the less visible overheads that can prevent SRAM compute-in-memory from scaling cleanly to useful precision: signed data, wires, accumulation logic, and internal switching.
As edge devices are asked to run larger neural networks within tight power budgets, eliminating external data movement is only part of the problem. Keeping the computation inside memory will matter most when the circuitry added to perform that computation does not quietly recreate the same energy penalty elsewhere on the die.
