IN Brief:
- TIER IV is developing an AI accelerator for Level 4 autonomous-driving workloads under a JST semiconductor R&D programme.
- The architecture targets Transformer inference, reduced external-memory traffic, and deployment from several-watt embedded devices to tens-of-watts vehicle ECUs.
- Chip logic, the compiler, and associated development tools are intended for open-source release.
TIER IV has joined a Japanese semiconductor research programme to develop an open AI processor architecture for Level 4 autonomous driving, extending its open-source approach from vehicle software into processor logic and the compiler technology around it.
The work forms part of the Japan Science and Technology Agency’s Next-Generation Edge AI Semiconductor Research and Development Program. TIER IV is responsible for logic design of an AI accelerator intended to handle end-to-end autonomous-driving inference, while a University of Tokyo research team led by Professor Yoshihiro Kawahara is investigating use-case-driven physical AI semiconductor design.
TIER IV plans to evaluate the processor as part of a system-on-chip and ultimately release the logic design, compiler, and associated development tools as open-source technology. The objective is to provide semiconductor manufacturers with an architecture that can be adapted for commercial SoCs rather than tie the programme to one proprietary silicon implementation.
The processor is being shaped around the demands of increasingly large autonomous-driving models. Transformer-based systems can process camera images, point-cloud data, and other sensor inputs across perception, prediction, and motion-planning tasks, but raw accelerator throughput is only one constraint inside a vehicle. Memory traffic, power consumption, latency, thermal limits, and deterministic system behaviour all influence whether the compute architecture is suitable for deployment.
TIER IV is therefore proposing dedicated circuitry for operations commonly used by Transformers, including matrix multiplication and attention functions. Its design also aims to reuse data within the processor rather than repeatedly moving it to and from external memory, reducing memory-access energy and some of the control overhead associated with more general-purpose architectures.
That data movement is particularly expensive at the edge. Modern AI models transfer substantial volumes of weights, activations, and intermediate results through the memory hierarchy, and the energy required to move those values can become a material part of the overall power budget. Keeping frequently accessed data closer to the compute blocks can improve performance per watt without depending solely on additional arithmetic units.
The planned architecture is not limited to one power envelope. TIER IV wants it to scale from embedded devices operating at several watts to in-vehicle electronic control units consuming several tens of watts, which places additional emphasis on portability between hardware configurations with different core counts, memory capacities, and thermal limits.
The software stack will use Tensor Operator Set Architecture, or TOSA, as an intermediate representation between AI frameworks and the processor. Models developed in frameworks such as PyTorch can be converted into that common representation before optimisation and code generation are applied for the target hardware.
This gives the compiler a larger role in maintaining compatibility as models and hardware evolve. Rather than binding one network architecture tightly to a fixed accelerator, TIER IV is aiming for a software-defined SoC approach in which compiler optimisation and hardware resources can change while retaining a common model representation.
The programme also includes formal verification of selected compilation stages. Translating a neural network for deployment can involve graph transformations, quantisation, rounding, and changes in numerical representation, all of which can alter calculations even when the objective is to preserve the original model’s behaviour.
TIER IV plans to use the defined TOSA operations to trace those transformations and assess whether numerical behaviour remains within specified tolerances. For automotive electronics, that creates a stronger link between accelerator performance and the traceability of the software chain used to produce the deployed workload.
The work extends the approach behind TIER IV’s Autoware platform into semiconductor design, but open RTL and compiler technology are still a considerable distance from qualified vehicle silicon. Physical implementation, functional safety, packaging, interfaces, manufacturing test, thermal design, and vehicle qualification remain necessary before a derivative SoC can enter a production ECU.
Opening the architecture nevertheless gives semiconductor developers a common starting point from which to optimise those implementations. If the programme produces usable logic, tooling, and verification methods, its value will be measured by whether commercial chip designers can adapt them without rebuilding the autonomous-driving compute stack around each new processor.
