Socionext adopts Intel 18A-P for custom SoCs

Socionext is extending its custom system-on-chip roadmap to Intel Foundry’s 18A-P manufacturing process, beginning with a high-performance compute chiplet for AI, edge, data-centre, and high-performance computing systems. The move adds another leading-edge process option to Socionext’s custom silicon portfolio as customers increasingly divide large computing architectures across specialised dies rather than attempting to place every function on one monolithic device.

The Japanese fabless semiconductor company plans to combine its ASIC architecture and implementation capability with Intel Foundry’s advanced process and packaging technologies. Socionext has not identified a customer for the first chiplet or disclosed die size, power, performance, packaging configuration, or production timing, but the workloads named for the programme place power delivery, thermal behaviour, memory bandwidth, and die-to-die communication among the likely architectural constraints.

Intel 18A-P is the performance-enhanced derivative of Intel 18A and retains the RibbonFET gate-all-around transistor architecture and PowerVia backside power delivery introduced with the base process. Intel says 18A-P entered risk production in June and remains compatible with 18A design rules, allowing engineering teams to reuse more of an existing implementation environment than would normally be possible when moving to a substantially different process.

Intel claims 18A-P provides around 9% higher performance at the same power or 18% lower power at equivalent performance compared with 18A. The process also introduces Power Boost, a dual-contact transistor option designed to increase drive current, alongside changes intended to improve thermal characteristics and reduce resistance within the interconnect and power-delivery structure.

Those details become increasingly important as custom processors move towards larger compute arrays and tighter power densities. A nominal transistor-speed improvement is of limited value if the completed die cannot deliver sufficient current or remove heat from active regions without reducing clock frequency. Backside power delivery separates more of the power-routing network from signal interconnect, giving physical-design teams another way to manage congestion and voltage drop at advanced geometries.

Socionext’s choice of a chiplet for the first development also reflects the changing economics of large SoCs. Partitioning a system across several dies can allow compute, I/O, memory interfaces, analogue functions, and accelerators to use process technologies better suited to each block, while potentially improving yield compared with building the entire system as one very large advanced-node die.

The trade-off moves engineering effort into the package. Die-to-die interfaces, power integrity, clock distribution, substrate routing, thermal coupling, known-good-die testing, and package yield all become part of the system architecture. A custom silicon supplier therefore needs more than access to a leading-edge wafer process if it expects to deliver chiplet-based products repeatedly.

Socionext describes its business around a Solution SoC model, combining architecture, customisation, implementation, and manufacturing relationships around a customer’s workload. Intel Foundry’s packaging roadmap is consequently relevant alongside 18A-P itself, particularly for systems expected to combine advanced compute dies with high-bandwidth memory or other chiplets in the same package.

The collaboration also gives Intel Foundry another external design engagement around the 18A family. Commercial foundry progress at an advanced node ultimately depends on customers moving beyond evaluation into tape-out, qualification, and recurring wafer demand, so Socionext’s first chiplet will be more significant once its production path becomes visible.

For Socionext, the process agreement broadens the manufacturing choices available to customers developing compute-intensive custom silicon. It does not remove the lengthy path from architecture to production: IP integration, verification, physical implementation, mask release, packaging, bring-up, software enablement, and qualification still have to be completed before the first device becomes a commercial product.

The immediate development is therefore less important as an isolated chip than as an indication of how Socionext intends to build future custom compute systems. Advanced process technology, packaging, and chiplet partitioning are becoming inseparable design decisions, and 18A-P gives the company another platform on which to make those decisions for customers whose workloads justify leading-edge silicon.