IN Brief:
- Plasma-induced sidewall damage becomes more severe as III-nitride micro-LED pixels shrink and perimeter effects dominate the active area.
- An in-situ dry repair and passivation process delivered 64.7% peak EQE in 2µm blue devices and 55.1% in green devices.
- The semiconductor-standard dry process could remove one manufacturing penalty as AR and VR microdisplays move towards smaller pixels.
Researchers led by Xiamen University have demonstrated an in-situ dry repair and passivation process that suppresses the size-dependent performance loss normally seen when III-nitride micro-LEDs are reduced to micrometre dimensions. The work addresses plasma-induced sidewall damage created during mesa etching, a process defect whose influence increases as pixel area shrinks.
The technique, described as in-situ dry repair and passivation, or IDRP, is integrated into the dry semiconductor process flow rather than added as a separate wet-treatment stage. Treated devices maintained strong electro-optical performance down to 1.6µm, while some structures showed a reversed size effect in which efficiency increased as dimensions were reduced.
For 2µm indium gallium nitride devices, peak external quantum efficiency reached 64.7% for blue micro-LEDs and 55.1% for green devices. The researchers also report higher manufacturing yield and greater electrostatic-discharge robustness, two practical measures that become increasingly important when millions of emitters have to operate within a narrow performance distribution.
The underlying defect mechanism is tied to the ratio between the active device and its etched perimeter. Dry etching is required to define the microscopic mesa, but the plasma process can leave damaged bonds, defects, and electrically active states around the exposed GaN sidewall. As the pixel becomes smaller, a larger share of the active region sits close enough to that damaged boundary for non-radiative recombination and leakage to affect efficiency.
IDRP is intended to repair the etched surface and passivate remaining states before fabrication continues. Measurements in the study show lower interface trap density, while the resulting carrier behaviour is consistent with reduced non-radiative loss. The process was applied across blue and green devices, supporting the case that the improvement is not confined to a single emission condition.
The research also includes a 0.39in nitride microdisplay demonstration, moving the result beyond isolated test structures. A display module still contains many manufacturing problems outside the LED mesa, but demonstrating an array is relevant because a process that improves only the best individual pixel has limited value if uniformity or yield deteriorates across a dense display.
Micro-LED development is increasingly shifting from headline brightness towards production behaviour. Recent ams OSRAM work has moved RGB micro-LED light engines closer to manufacturing readiness, particularly for augmented-reality systems where efficiency, pixel density, optical coupling, and thermal limits have to be solved within a very small module.
AR and VR displays are among the harsher applications for the emitter because light is lost through waveguides and other optics before reaching the eye. Smaller pixels can raise resolution and reduce engine size, but those benefits diminish if shrinking the mesa imposes an efficiency penalty. Sidewall damage therefore sits directly between lithographic scaling and usable optical output.
The IDRP route is notable because it uses a semiconductor-standard dry process, reducing the need to introduce another wet chemistry sequence around a fragile, densely patterned wafer. That does not make the technique production-ready by itself: plasma uniformity, chamber condition, wafer loading, passivation repeatability, and compatibility with later metallisation and bonding steps will all need to hold across production-scale lots.
Other parts of the micro-LED manufacturing chain remain difficult. Epitaxial uniformity, colour integration, mass transfer or monolithic integration, backplane connection, defect repair, optical extraction, and final test can each set the yield ceiling independently of sidewall performance. Improvements in one stage only become valuable when they survive the remainder of that chain.
The reported EQE figures nevertheless remove an important assumption from the scaling discussion: micrometre dimensions do not have to impose the same efficiency collapse if etch damage is treated as a process problem rather than an unavoidable geometric penalty. The next test is statistical rather than spectacular — whether the same gains persist across larger wafers, production tools, and the pixel populations needed for commercial microdisplays.
