IN Brief:
- AI compute throughput is increasing faster than electrical interconnect bandwidth, shifting bottlenecks beyond individual accelerator packages.
- SK hynix's CPO roadmap targets more than 100Tb/s per node, below 1pJ/bit, and sub-10ns chip-to-chip latency.
- Longer-term concepts extend optical links towards pooled memory through photonic interposers and heterogeneous packaging.
SK hynix has published a co-packaged optics roadmap that extends its AI infrastructure work beyond high-bandwidth memory and into the interconnects linking processors, memory, racks, and pods. Developed with researchers from several universities, the work sets out how photonics, advanced packaging, and memory architecture could co-evolve as electrical data movement becomes a larger system constraint.
The paper starts from a widening scaling gap. SK hynix says compute throughput has typically tripled every two years while interconnect bandwidth has increased about 1.4-fold over the same period, leaving system performance increasingly dependent on how quickly data can move between processors and memory rather than on the capability of an individual accelerator package.
Co-packaged optics shortens the highest-speed electrical path by moving optical engines close to the processor package and using light for the longer connection. Copper remains economical over short distances, but insertion loss, equalisation power, routing density, and latency become progressively harder to manage as lane rates and reach increase.
The roadmap sets targets above 100Tb/s of bandwidth per node, energy consumption below 1pJ/bit, and chip-to-chip latency below 10ns. It describes a progression through 2D and 2.5D interposer arrangements towards 3D heterogeneous integration, placing photonic and electronic functions closer together as package density increases.
Those targets make packaging part of the interconnect architecture rather than a mechanical step after the optical design is finished. Laser coupling, fibre attach, optical alignment, thermal behaviour, electrical driver placement, yield, test, and repair all have to coexist with expensive processors and memory stacks. A photonic engine that meets a laboratory link budget but cannot survive high-volume assembly offers little advantage to a data centre operator.
SK hynix’s longer-term proposal extends optical connectivity towards memory itself. The optics-centric architecture uses a photonic interposer to connect compute resources with pooled memory through optical links, allowing several accelerators to access a larger memory resource without relying solely on long electrical connections between packages and boards.
That concept complements HBM rather than replacing it. HBM provides very high bandwidth close to the accelerator through stacked DRAM and wide local interfaces, but a large AI system still has to move data between accelerators, switches, racks, and memory resources. Once those transfers dominate application performance, improving only the memory attached to one processor no longer resolves the complete data movement problem.
Optical-interconnect suppliers are already taking shorter-reach alternatives into customer evaluation. Avicena is shipping 1Tbps micro-LED optical-interconnect evaluation kits using hundreds of parallel channels, giving system developers another route to move optics progressively closer to compute silicon. The architectures are different, but the manufacturing questions around alignment, power, thermal stability, and dense packaging are beginning to converge.
The electrical budget around the optical engine remains important. Drivers, transimpedance amplifiers, clocking, control, and SerDes functions still consume power and silicon area, while the package must route high-speed electrical signals far enough to reach the photonic interface. The system case depends on whether shortening those electrical paths saves more power and complexity than the optical packaging introduces.
Commercial deployment also needs coherence, serviceability, and reliability to mature alongside aggregate bandwidth. Optical functions placed deep inside a compute package are harder to replace than conventional pluggable transceivers, so failure rates and manufacturing yield become especially expensive. Thermal cycling beside processors and HBM stacks adds another qualification burden for materials and optical alignment.
SK hynix is entering that discussion because future memory performance increasingly depends on the interconnect around the memory as much as on the DRAM itself. HBM has relieved one bandwidth bottleneck inside the accelerator package; the roadmap identifies the next one between packages, boards, racks, and pooled memory, where copper has progressively less comfortable electrical margin.
