IN Brief:
- Advanced semiconductor process development increasingly depends on equipment, feature-scale, and structural simulations sharing consistent manufacturing data.
- Silvaco Victory Process will connect with Dassault Systèmes SIMULIA tools for plasma, stress, deformation, and related multiphysics analysis.
- The companies intend to reduce model reconstruction and narrow physical experimentation during process development and yield ramp.
Silvaco and Dassault Systèmes are developing interoperable semiconductor manufacturing workflows that connect equipment-scale plasma simulation, feature-scale process modelling, and structural analysis. The collaboration is intended to preserve engineering data as it moves between simulation environments, reducing repeated model reconstruction before process changes reach fabrication equipment.
The first planned workflow links plasma simulation in Dassault Systèmes’ SIMULIA applications with Silvaco Victory Process. Engineers will be able to model the relationship between reactor conditions and the evolution of semiconductor features during plasma-based etch and deposition, rather than treating equipment physics and wafer geometry as separate studies.
A second workflow will transfer semiconductor structures and material information generated by Silvaco into SIMULIA structural-analysis environments. That adds stress, deformation, and related mechanical behaviour to a chain that begins with equipment conditions and continues through the geometry created on the wafer.
Process simulation has long been part of semiconductor development, but individual models often stop at disciplinary boundaries. A reactor model may describe plasma chemistry and transport, while a process simulator calculates feature evolution and another tool handles stress or deformation. Rebuilding geometry and material definitions at each stage consumes engineering time and can discard information needed to understand why a downstream result changed.
The proposed interfaces are intended to retain that relationship. If an adjustment to plasma conditions changes sidewall profile or film thickness, the resulting feature can move directly into subsequent structural analysis rather than being reconstructed manually. That makes it easier to trace an observed stress or deformation result back to the process condition that produced it.
The approach becomes more relevant as device structures grow more three-dimensional. Gate-all-around transistors, vertical memory, heterogeneous devices, advanced power semiconductors, and complex interconnect stacks combine narrow process windows with materials whose mechanical and electrical behaviour are closely coupled. A change that improves one fabrication step can create another problem several stages later.
Physical experimentation remains necessary, but each wafer split consumes equipment time, materials, metrology capacity, and engineering effort. Narrowing the number of process conditions that have to be tested in hardware can shorten development cycles, particularly during technology ramp when several process variables are being tuned at once.
Simulation quality still depends on calibration. Plasma models need accurate chamber, chemistry, and boundary-condition data, while feature-scale and structural models rely on material properties that may themselves change with deposition conditions. Connecting several models does not remove those uncertainties; it gives engineers a more systematic way to carry them through a manufacturing sequence.
Traceability is another practical advantage. Semiconductor process development frequently involves several engineering teams working across equipment, integration, device, and reliability functions. A connected model can provide a shared representation of how an upstream change alters downstream geometry or stress, reducing the risk that the same problem is investigated independently from several different starting points.
Silvaco and Dassault Systèmes are describing the work as a foundation for broader semiconductor manufacturing digital twins. The term has been applied rather loosely across manufacturing software, but here the useful element is specific: linking simulations at different physical scales so that equipment conditions can be followed through to wafer and structural outcomes.
The companies also expect the workflow to help engineers evaluate more alternatives before committing them to the fab. That becomes increasingly valuable when experimental cycles involve advanced lithography, deposition, etch, or integration equipment with high operating costs and limited engineering availability.
There is no suggestion that virtual process development will replace silicon validation. Models remain representations of real equipment and materials, and deviations between the two have to be measured continuously. The engineering gain comes from using simulation to eliminate poor options earlier, leaving expensive wafer experiments to test a narrower and better-understood set of process conditions.
Semiconductor manufacturing already generates enough simulation data. Silvaco and Dassault Systèmes are concentrating on the less glamorous difficulty of making those models exchange useful information without an engineer repeatedly rebuilding the same wafer structure in another software environment.
