IN Brief:
- pPLL03 supports integer-N and fractional-N clock synthesis at frequencies up to 4GHz.
- Perceptia specifies 5.25ps peak period jitter at 4GHz and an implementation area of 0.0071mm².
- The immediately available kit includes simulation, timing, layout, netlist, and characterisation files.
Perceptia Devices has released a design kit for its pPLL03 phase-locked loop on Samsung Foundry’s 14LPU process, giving system-on-chip designers a clock-generation block operating at frequencies up to 4GHz.
The IP supports both integer-N and fractional-N synthesis and is aimed at processors, AI accelerators, high-speed digital logic, and sampling clocks for ADCs and DACs. Perceptia specifies peak period jitter of 5.25ps at 4GHz, equivalent to less than 2.1% of a clock cycle.
The 14LPU implementation occupies 0.0071mm² and incorporates power-conditioning circuitry intended to improve PLL behaviour in electrically noisy SoC environments. Perceptia also specifies operation across process, voltage, and temperature extremes rather than limiting its published performance to nominal conditions.
Lock time is quoted at 400 reference-clock cycles. The design provides fractional output division with six-bit resolution and glitch-less transitions, allowing operating frequencies to change without an uncontrolled clock discontinuity.
That makes the block relevant to systems using dynamic frequency scaling, where processors or accelerators adjust clock rates according to workload or power limits. The useful engineering trade-off is not simply maximum frequency, but how accurately and predictably the PLL can move between operating points while maintaining sufficient clock quality for the surrounding logic.
Julian Jenkins, chief technology officer at Perceptia, said: “Our goal with pPLL03 was to bring our best-in-class jitter performance with integration flexibility to Samsung Foundry 14LPU.”
A PLL occupies relatively little silicon compared with a processor core or large memory array, but errors in its output propagate throughout the circuitry using that clock. Excessive jitter reduces timing margin in digital logic and can degrade signal quality in data-converter and high-speed interface applications.
Fractional-N operation gives designers greater freedom in generating frequencies that are not simple integer multiples of the reference clock. That can simplify a system clock tree and reduce the number of external references, although fractional synthesis also requires careful design to control noise and spurious tones.
Direct comparisons between PLL specifications need some care because jitter figures depend on measurement method, output frequency, loading, and bandwidth. The more useful point in Perceptia’s announcement is that the company has characterised and packaged the block specifically for Samsung’s 14LPU process rather than simply advertising an architecture available elsewhere.
Analogue and mixed-signal IP cannot be moved between semiconductor processes as casually as synthesised digital logic. Transistor characteristics, parasitic capacitance, supply behaviour, passive components, and physical layout all influence PLL performance, which means each process implementation requires design and characterisation work.
The supporting kit is consequently as important as the headline clock rate. Perceptia is providing Liberty timing models, Verilog and Verilog-A simulation models, GDSII and LEF physical views, a CDL netlist, layout constraints, integration guidance, and verification and characterisation data.
Those files allow the block to enter established SoC implementation and verification flows. Physical-design engineers need accurate abstract views and constraints, while simulation and timing teams need models that reflect the behaviour of the actual implementation rather than a generic description of the circuit.
Perceptia uses an all-digital control interface around the PLL, allowing configuration to be driven by digital logic or software. That can simplify integration where firmware or a power-management controller changes operating frequencies according to system state.
Samsung 14LPU is a mature FinFET process rather than the foundry’s most advanced node, which is not necessarily a disadvantage for mixed-signal SoCs. Established process technologies can offer a more mature IP ecosystem and different cost, analogue, yield, and qualification trade-offs from leading-edge digital nodes.
The pPLL03 release should therefore be judged as a specific IP-availability milestone rather than a wider shift in semiconductor clocking. Qualified Samsung 14LPU customers can now integrate the block with published area, jitter, lock-time, and PVT data, which is the information needed before a PLL stops being a datasheet idea and becomes part of an actual SoC clock plan.