TSMC maps two paths for COUPE bandwidth

TSMC has detailed two routes for increasing the bandwidth of its Compact Universal Photonic Engine, extending the foundry’s silicon-photonics roadmap as data movement becomes a larger constraint around AI processors and accelerator clusters.

Ming Fa Chen, deputy programme director at TSMC and head of its Photonics Packaging Integration work, presented the latest COUPE development at the Silicon Photonics Global Summit in Taiwan. The roadmap addresses both the speed of individual optical channels and the number of channels and wavelengths that can be combined within the photonic engine.

The first route increases per-channel data rates while expanding channel count. TSMC is working from 200Gbps operation towards more than 400Gbps per channel, while moving from 16 channels to more than 128. Aggregate bandwidth would consequently rise from around 3.2Tbps towards levels above 12.8Tbps.

The second route increases wavelength-division multiplexing, progressing from a single optical wavelength towards four, eight, 16, and eventually more wavelengths. Multiple data streams can then share the same optical path, allowing bandwidth to increase without relying entirely on additional fibres or physical channels.

The two approaches impose different engineering penalties. Faster channels require higher-performance modulators, receivers, drivers, and electrical interfaces, while additional wavelengths increase demands around laser sources, wavelength control, filters, optical power, and thermal stability. Combining both methods can raise aggregate throughput substantially, but it concentrates more complexity inside the photonics and packaging system.

COUPE is based on close integration between electronic and photonic integrated circuits using TSMC’s SoIC bonding technology. The company has demonstrated bonding pitches in the 2µm to 4µm range, shortening the electrical path between the electronic IC and photonic IC before data is converted into the optical domain.

TSMC has reported transmission loss of approximately 0.06dB at 112Gbps across the fine-pitch interface, compared with around 1.38dB for the micro-bump arrangement used as its reference. Reducing that loss matters because energy consumed moving data between the electrical driver and the optical device adds power and heat without increasing the useful reach of the final optical link.

The foundry had already established a staged production route for COUPE. Its on-substrate implementation is scheduled to enter production during 2026, moving the optical engine from a conventional pluggable position on the circuit board into the semiconductor package. TSMC has associated that configuration with a 200Gbps micro-ring modulator and improvements in both latency and power efficiency compared with pluggable optics.

The latest roadmap moves beyond that first production stage. TSMC is examining heterogeneous integration in which modulators, semiconductor optical amplifiers, and light sources can be placed directly onto the rear of the COUPE platform, while the photonic engine can also operate as an optical interposer spanning an area of up to approximately 3.3 reticles.

Moving optical conversion closer to the compute silicon reduces the length of the highest-speed electrical link. Pluggable optics can carry data efficiently between systems, but signals still travel electrically between the switch ASIC or processor and the optical module. Near-packaged and co-packaged approaches shorten that electrical section from board-level distances towards package-level interconnects.

Open co-packaged-optics architectures are simultaneously trying to standardise the interfaces between switches, optical engines, fibres, external lasers, and packaging. That work becomes more important as CPO moves beyond demonstrations and into equipment that has to be manufactured, tested, cooled, repaired, and replaced in volume.

Wavelength multiplexing makes those production requirements more demanding. Each additional wavelength increases the need for spectral control and stable optical components, while laser systems positioned close to high-power compute hardware must maintain useful output across changing thermal conditions. Test equipment also has to verify electrical performance, optical power, wavelength alignment, insertion loss, and channel behaviour without making final package test prohibitively expensive.

Yield becomes increasingly important as more functions are brought into one assembly. A CPO package can combine an expensive switch or compute die with photonic devices, advanced substrates, fibre connections, and external or integrated laser hardware. Discovering a defect only after those elements have been assembled carries a much higher cost than rejecting an individual die or optical component earlier in production.

Similar optical-link development around processors and memory shows how the bandwidth problem is spreading beyond conventional network switches. AI systems increasingly need to move data between accelerators, memory pools, racks, and complete compute pods, making energy per bit and latency system-level design constraints.

TSMC’s advantage is that COUPE is being developed alongside its SoIC and CoWoS packaging technologies rather than as an isolated photonics process. That creates a route to integrate logic, memory, photonics, and package interconnects through a common manufacturing ecosystem, although it also increases the number of variables that must be controlled simultaneously.

The immediate milestone remains the 2026 production introduction of COUPE on substrate. Beyond that, TSMC is targeting faster channels, many more channels, higher wavelength counts, and optical functions placed progressively closer to the processor package. Achieving the headline bandwidth is only part of the task; maintaining yield, thermal stability, optical alignment, and economical test at that density will determine whether the architecture scales commercially.