IN Brief:
- FlexGen Multi-Die extends Arteris NoC connectivity across physical die boundaries for non-coherent AI and HPC architectures.
- Bidirectional traffic can share a single UCIe PHY, which Arteris says can cut associated PHY area, power, and I/O requirements by up to 50%.
- The wider portfolio combines FlexGen Multi-Die, Ncore Multi-Die, Magillem integration automation, and Cycuity hardware-security assurance.
Arteris has expanded its multi-die interconnect portfolio with FlexGen Multi-Die, extending network-on-chip functions across physical chiplet boundaries for non-coherent AI and high-performance computing architectures.
The IP is designed to help semiconductor teams partition increasingly large systems across several dies without rebuilding the data-movement architecture around every new boundary. Functions normally handled inside a monolithic SoC, including traffic management and quality of service, can therefore be extended over die-to-die links.
That capability is becoming more important as accelerator, processor, memory-interface and I/O functions are split across chiplets. Large AI devices can approach the practical manufacturing limits of a single die, while separate chiplets also allow different process technologies to be used where they provide the best balance of cost, density, analogue performance or I/O capability.
The trade-off is that communication which once travelled across on-die wiring must now pass through a physical package interface. Bandwidth, latency, die-edge area, I/O count and power become part of the system architecture rather than implementation details hidden inside one piece of silicon.
FlexGen Multi-Die addresses non-coherent architectures, complementing Arteris’ Ncore Multi-Die technology for cache-coherent systems. It carries NoC traffic-management behaviour across UCIe-connected dies so that priority and quality-of-service policies can continue to operate when a transaction leaves one chiplet and enters another.
Arteris says bidirectional transactions can share a single UCIe PHY, reducing the amount of interface hardware required for communication in both directions. Under its stated comparison, the approach can cut associated PHY area, power and I/O requirements by as much as 50%.
That reduction is relevant because chiplet edges are a limited resource. A multi-die device may need memory interfaces, high-speed external I/O, power delivery and die-to-die communication around the same perimeter, so every additional PHY competes for package routing and physical space.
Virtual-channel link technology is also used to improve utilisation of the available die-to-die connection. Quality-of-service mechanisms can then protect higher-priority traffic when several flows contend for the same physical path.
AI accelerators make that problem particularly visible. Model weights, activations, control traffic and memory requests can have different bandwidth and latency requirements, and poor arbitration between those flows can undermine the performance expected from adding more compute resources.
Once data crosses a chiplet link, the NoC architecture has to account for the behaviour of the die-to-die PHY and package as well as internal arbitration. The interconnect can no longer be treated independently from packaging and physical implementation.
Arteris is positioning FlexGen Multi-Die inside a broader multi-die design flow rather than as a standalone interface block. The company’s portfolio includes Ncore Multi-Die for coherent systems, Magillem technology for IP packaging and integration, and Cycuity tools for hardware-security assurance.
The objective is to preserve more of the design methodology already used for complex SoCs as developers move into chiplets. A mature NoC represents substantial investment in topology, arbitration, performance modelling and verification, so carrying those concepts across die boundaries is potentially less disruptive than redesigning the communication architecture from first principles.
Reuse becomes still more valuable where several products share common compute or I/O chiplets. A standard interconnect framework can allow those building blocks to be recombined across devices while maintaining established data-movement behaviour, although package constraints and workload-specific bandwidth will continue to limit how modular the finished architecture can become.
UCIe provides a common physical and protocol foundation for die-to-die communication, but it does not by itself solve traffic management, memory behaviour or system-level verification. Those layers remain the responsibility of the semiconductor architecture around the link.
FlexGen Multi-Die is available to early-access partners and strategic customers. Its practical value will be measured by whether established NoC behaviour can be preserved across UCIe-connected dies without introducing enough integration overhead to offset the development advantages chiplets are intended to provide.
