IN Brief:
- Micron has demonstrated a 512GB DDR5 RDIMM across several next-generation server platforms.
- Vertically stacked DRAM dies use through-silicon vias, enabling up to 12TB in a 24-slot dual-socket server.
- AMD and Intel are validating the module, with volume production targeted for the second half of 2027.
Micron has demonstrated a 512GB DDR5 registered DIMM across several next-generation server platforms, using vertically interconnected DRAM packaging to increase memory capacity without adding motherboard slots.
The module is designed to reach transfer rates of up to 9,200MT/s and uses stacked DRAM dies connected by through-silicon vias. Micron says the resulting density could allow a 24-slot dual-socket server to carry as much as 12TB of directly attached DDR5 memory.
AMD and Intel are validating the module for future server platforms, while Micron expects volume production during the second half of 2027. The current milestone is therefore a platform demonstration rather than immediate commercial availability.
The density increase addresses a growing imbalance in high-end computing. Processor core counts and accelerator throughput are rising quickly, but those compute resources deliver little benefit if the working dataset cannot be held close enough to the processor or supplied at the required bandwidth.
A 512GB RDIMM doubles the capacity of a 256GB module while preserving the established DDR5 DIMM architecture. That gives server designers a route to larger memory footprints without increasing slot count or immediately moving the workload onto a separate memory tier.
Applications including in-memory databases, virtualisation, analytics, simulation and AI inference can all benefit when larger datasets remain resident in DRAM rather than being moved repeatedly to slower storage.
The packaging technology is central to the development. Micron vertically stacks DRAM dies and connects them through silicon vias inside the package, increasing capacity without simply enlarging the DIMM PCB or adding more conventional packages along the module.
TSV-based stacking is already established in high-performance memory technologies, but using it to build very high-capacity DDR5 RDIMMs brings advanced packaging into an otherwise familiar server-memory form factor.
Power consumption becomes an important consideration as density rises. Micron says one 512GB module operates at 16W under its stated comparison, against 44.2W for four 128GB RDIMMs providing the same nominal capacity. That corresponds to a reduction of more than 60%.
The comparison does not mean every server can simply replace four lower-capacity modules with one larger device without considering channel population and bandwidth. Server-memory architecture depends on how DIMMs are distributed across memory channels, so capacity, bandwidth and power still have to be balanced at platform level.
It does show the electrical attraction of placing more memory behind fewer modules. Each populated DIMM adds its own buffer, signalling and power overhead, so increasing density can reduce some of the fixed consumption associated with achieving a given total capacity.
Micron also reports up to 1.4 times higher performance for a Spark Support Vector Machine analytics workload compared with 256GB DDR5 configurations. That result is application-specific, but it illustrates how capacity can affect performance when a larger active dataset remains in memory.
The development sits alongside wider changes to the server memory hierarchy. In August, Primemas detailed a CXL architecture using Micron DDR5 to create memory pools exceeding 100TB per rack.
CXL and ultra-dense local DIMMs solve different parts of the capacity problem. Larger directly attached DDR5 preserves the latency and software model of conventional main memory, while CXL allows capacity to expand or become more independent from the processor’s own memory channels.
Those approaches are likely to coexist as systems become more heterogeneous. Latency-sensitive workloads may favour the largest practical directly attached memory population, while capacity-heavy applications can use additional tiers where the performance trade-off is acceptable.
AMD and Intel validation will be significant beyond simple electrical compatibility. Memory-controller behaviour, firmware, training, thermal limits and signal integrity all become more demanding as module density and transfer rate increase.
Micron’s second-half 2027 production target leaves another development cycle before the 512GB RDIMM becomes a volume server component. The demonstration nevertheless shows how advanced DRAM packaging is being used to extend the useful capacity of conventional DDR5 infrastructure rather than forcing every memory-bound system towards a completely different architecture.
