IN Brief:
- The $52 million programme is SEMIFIVE’s largest single contract and its first North American Spec Hand-off engagement.
- The inference accelerator will use LPDDR6 and PCIe Gen5, with SEMIFIVE responsible for design, software, packaging, testing and production.
- Tape-out is targeted for the first half of 2027, followed by global mass production beginning in 2028.
SEMIFIVE has secured a $52 million contract to develop a next generation AI inference accelerator for an unnamed US fabless semiconductor company, taking responsibility from system specification through to eventual mass production.
The programme is SEMIFIVE’s first North American engagement under its Spec Hand-off model and its largest single contract to date. Rather than receiving a substantially completed chip design for implementation, the company will begin with the customer’s performance requirements and specifications before carrying the device through detailed design, software development, packaging, testing and production.
The contract is worth approximately KRW70.3 billion. SEMIFIVE says that represents more than 40% of its total 2025 orders of KRW168.4 billion and around 60% of the KRW118.9 billion in new orders booked during the first half of 2026, making successful execution commercially significant as well as technically demanding.
The accelerator is intended for large scale AI inference and will use LPDDR6 memory alongside PCIe Gen5 connectivity. SEMIFIVE has not disclosed the customer, process node, package architecture, memory channel count or peak compute performance, leaving the current programme defined primarily by its interfaces, intended workload and development scope.
LPDDR6 is intended to provide higher memory bandwidth while controlling memory power consumption, an increasingly important constraint in inference systems processing large models. Accelerator performance can be limited when compute engines cannot receive model weights and intermediate data quickly enough, so usable memory bandwidth depends on the complete controller, channel, package and software architecture rather than the nominal DRAM data rate alone.
PCIe Gen5 provides the host connection, creating a well established route into server and cloud infrastructure. The interface can carry large volumes of data between the accelerator and host system, although sustained accelerator utilisation also depends on how workloads are partitioned and how much information can remain resident in local memory rather than repeatedly crossing the PCIe link.
SEMIFIVE describes the project as a Big Die implementation and points to previous designs reaching die areas of up to 800mm². Large monolithic dies can accommodate substantial compute resources and memory interfaces, but increasing die area also raises manufacturing pressure because random wafer defects have a greater opportunity to affect each finished device.
Physical implementation consequently becomes closely tied to commercial yield. Power delivery, clock distribution, floorplanning, thermal behaviour and package design all have to be resolved across a large area while maintaining acceptable manufacturing yield. A high performance architecture that produces too few usable dies can quickly lose its economic advantage.
The Spec Hand-off arrangement places those decisions inside a broader engineering responsibility than a conventional implementation contract. Architecture choices made near the start of the programme influence RTL development, verification, physical design, packaging, firmware and production test, while software development has to progress early enough to support silicon bring-up once the first devices return.
That extends the role SEMIFIVE has already been building through its expanding ASIC development and production pipeline. The new contract begins further upstream than those production bookings, with the company expected to translate application requirements into the semiconductor architecture itself.
Tape-out is targeted for the first half of 2027. First silicon will then have to pass bring-up, functional validation, package qualification and system testing before global mass production begins in 2028, leaving little room for fundamental architectural changes once the physical design approaches completion.
Custom inference silicon can justify that development commitment when deployment volumes and workload stability are sufficient. Removing functions that a specific service does not need can improve power, cost or throughput compared with a general purpose accelerator, but the resulting device is less able to absorb major changes in model architecture after its hardware has been fixed.
The programme therefore combines a large commercial commitment with a long technical dependency chain. SEMIFIVE has secured responsibility from specification to manufacturing; tape-out in the first half of 2027 will provide the first hard indication of whether that wider development model has translated the customer’s inference requirements into manufacturable silicon.
