IN Brief:
- Murata's LLD series puts a three-terminal low-ESL MLCC into a 0.6×0.3mm 0201-inch package.
- Mounting area falls by approximately 64% compared with the company's previous 1.0×0.5mm three-terminal device.
- The lower-inductance structure is intended to suppress high-frequency supply-voltage variation close to high-speed ICs.
Murata Manufacturing has begun mass production of its LLD series three-terminal low-ESL multilayer ceramic capacitors in a 0201-inch, or 0.6×0.3mm, package. Murata describes the devices as the world’s smallest three-terminal low-ESL MLCCs, based on its own research as of 29 September 2026.
The package reduces mounting area by approximately 64% compared with Murata’s previous smallest three-terminal device, which uses a 0402-inch, or 1.0×0.5mm, footprint. The company is targeting power stabilisation around increasingly fast and densely integrated ICs, initially highlighting compact equipment such as smartphones and wearables.
The electrical advantage comes from the three-terminal structure rather than miniaturisation alone. A conventional two-terminal capacitor carries current between two opposing terminations, while a three-terminal device is arranged so that current flows through a shorter and more controlled path. That structure reduces equivalent series inductance, allowing the capacitor to remain effective further into the high-frequency region.
Lower inductance becomes increasingly important as processor current changes over shorter time intervals. An IC can move rapidly between operating states, creating transient demand that the power delivery network has to satisfy before the supply voltage moves outside its permitted range. Bulk capacitance provides stored energy, but parasitic inductance in the capacitor, package, vias, planes, and interconnect can prevent that charge reaching the load quickly enough.
Low-ESL capacitors address part of that path by reducing the inductive contribution of the component itself. Their effectiveness still depends on placement. A capacitor positioned several centimetres from the IC can lose much of its high-frequency advantage through PCB inductance, which is why the reduction to a 0.6×0.3mm body has value beyond simply increasing component density.
A smaller package gives layout engineers more freedom to position the device close to the processor or other high-speed load. It can also release routing space around ball-grid-array packages where power pins, signal escape routes, vias, and local decoupling compete for a limited amount of board area. The 64% mounting-area reduction therefore affects both component count and the geometry of the power distribution network.
Murata says the miniaturisation required changes to electrode design and manufacturing technology. Three-terminal MLCCs have a more complex electrode structure than ordinary two-terminal devices, so retaining the low-inductance current path while reducing the ceramic body places tighter constraints on internal geometry and production accuracy.
The announcement marks the product as a mass-production component rather than a laboratory sample. That gives designers the option to compare the LLD series with existing 0402 three-terminal devices in actual impedance measurements, transient-load testing, and board-level reliability work rather than relying only on simulated package behaviour.
Those comparisons will be particularly useful because reducing package dimensions can introduce other design considerations. Assembly tolerances become tighter, pad design becomes more sensitive, and manufacturing yield can be affected if placement accuracy, solder volume, or board warpage are not well controlled. The electrical gain therefore has to be considered alongside the production process required to place the device reliably.
The technology also has applications beyond the compact consumer equipment highlighted by Murata. Embedded compute modules, communications hardware, industrial processors, accelerator cards, and other densely populated electronics face the same underlying problem as IC speeds rise: supplying rapidly changing current without allowing local rail impedance to create excessive voltage variation.
A three-terminal MLCC will not replace the complete decoupling network, since different frequencies and energy requirements still call for combinations of capacitance values and package types. Murata’s 0201 format instead reduces the board-area penalty associated with adding a particularly low-inductance element near the load, giving engineers more freedom to shape the high-frequency end of the power distribution network without surrendering as much PCB space.
