IN Brief:
- The E1L uses eight, sixteen or twenty-two Arm Neoverse N2 cores and supports networking up to 200 Gbps.
- The eight-core 100 Gbps configuration has a 25 W TDP and 15 W typical power figure.
- Xsight plans sampling in the second quarter of 2027; the devices are not yet generally available.
Xsight Labs has unveiled the E1L, an Arm-based data processing unit intended to take networking, storage and security work away from host processors in infrastructure equipment with limited power and cooling capacity.
The company announced the new E-Series device on 8 October and expects initial sampling in the second quarter of 2027. The range supports eight, sixteen or twenty-two Arm Neoverse N2 processor cores, with up to 200 Gbps of networking capability depending on the selected configuration.
The minimum 25 W thermal design power applies to the eight-core, 100 Gbps configuration, for which Xsight also specifies 15 W typical consumption. Other variants have 30 W or 40 W TDPs, with corresponding typical power figures of 18 W or 25 W. These values should not be conflated with measured power under every workload.
A DPU runs infrastructure software in a separate processing environment instead of leaving all packet processing, network protection and storage functions to the main server CPU. In practice, the benefits depend on the workload that can be transferred and how the host and DPU exchange data.
Xsight bases E1L on Arm Neoverse CSS N2 and the TSMC N5 semiconductor process. The processor cores provide a programmable execution environment, while the surrounding hardware supports high-bandwidth connectivity and acceleration for work that may otherwise consume general-purpose computing resources.
The product family provides up to 200 Gbps of networking through four high-speed serial lanes. That maximum belongs to appropriately configured products and does not mean every E1L installation can sustain the same throughput under arbitrary packet sizes, security settings or software workloads.
Memory connectivity includes as many as two DDR5-5200 interfaces with inline encryption. Host connectivity supports twenty PCI Express Gen5 lanes through six dual-mode controllers, with single-root I/O virtualisation for sharing device resources between compatible environments.
The design also includes AES-GCM acceleration aimed at IPsec network security processing. Cryptographic offload can free processor cycles when substantial amounts of encrypted traffic move through a system, although throughput remains dependent on packet sizes, system configuration and the use of hardware acceleration by software.
The software architecture is intended to work with established Linux distributions and infrastructure frameworks. Xsight lists Express Data Path, the Data Plane Development Kit and the Storage Performance Development Kit among supported integration technologies, aiming to avoid a separate proprietary programming environment.
Using established frameworks may make it easier to transfer software between E1L and the larger E1 DPU. It does not automatically guarantee that an application written for a higher-throughput device will meet its performance target within a much smaller processor and power budget.
Equipment designers must also plan the thermal interface for the selected configuration. Thermal design power is a component-level planning measure; enclosing the device in a compact appliance changes the available airflow, heat rejection and other conditions affecting sustained operation.
Xsight identifies edge computing, embedded infrastructure and power-constrained sites as target environments. Such equipment may have to perform encrypted communications and storage services without the space or cooling resources commonly available in large data centre servers.
The company plans to offer the technology as a discrete device, a COM Express module and a 1U server. These are intended configurations announced alongside the roadmap rather than evidence of volume supply or completed customer qualification.
Xsight will present the E1L during the Open Compute Project Global Summit in October. That demonstration is separate from the stated sampling timetable and should not be interpreted as confirmation that the semiconductor is already shipping commercially.
For design teams, detailed evaluation will require sample hardware, device documentation, software validation and tests under representative networking, encryption and storage loads. The October launch establishes the architecture and proposed performance envelopes, with practical results to be established during customer evaluation.
