IN Brief:
- BOS Semiconductors is joining MIRISE Technologies’ automotive chiplet interconnect research.
- MIRISE is owned 51% by DENSO and 49% by Toyota Motor Corporation.
- The work is research and prototyping; neither production silicon nor a vehicle launch is announced.
South Korean semiconductor developer BOS Semiconductors has been selected to support an automotive chiplet interconnect research programme led by Japan’s MIRISE Technologies, contributing its experience in system-on-chip design and modular semiconductor architectures. The collaboration will focus on research and prototyping of interconnect technologies intended for future vehicle computing systems, rather than immediate development of a named production processor.
MIRISE Technologies was established in April 2020 by DENSO and Toyota Motor Corporation to combine semiconductor research capabilities. DENSO holds a 51% stake and Toyota the remaining 49%, with the company concentrating on technology relevant to electric vehicles, automated driving and advanced mobility applications. The programme brings in BOS as a partner with experience designing automotive computing architectures using multiple semiconductor components.
By dividing a larger semiconductor into smaller dies connected within one package, chiplet architectures can combine components fabricated using different technologies. The arrangement allows designers to consider different manufacturing processes for different functions, potentially combining processors, accelerators, interfaces and other circuitry without requiring all to be fabricated with the same technology.
Separating a system into multiple dies introduces communication and packaging requirements different from internal wiring of a conventional monolithic semiconductor. Data, control signals and electrical power must cross boundaries between dies, while connections need sufficient bandwidth and suitably low latency for intended applications. Requirements become more demanding when individual chiplets exchange large volumes of information or coordinate processing tasks under strict timing constraints.
MIRISE and BOS are investigating how automotive chiplets could communicate across package boundaries, drawing on BOS’s system-on-chip design experience. The partners have not disclosed the die-to-die interface standard, target bandwidth, connection geometry or fabrication processes under evaluation. The activity therefore remains research and prototyping rather than a defined production chip programme.
Camera perception and automated driving require substantial processing throughput, whereas many vehicle control functions also depend on predictable response times and managed fault behaviour. Communication between separate chiplets must accommodate both kinds of workload without allowing traffic contention or timing variability to undermine the time-sensitive functions.
Die-to-die interconnects influence those trade-offs because movement of information between chiplets consumes energy and introduces electrical paths. Communication structures suitable for an accelerator may need different signalling and buffering arrangements from those connecting lower bandwidth control functions. Physical arrangement of chiplets, number of connections and available power and thermal budgets influence implementation.
The physical position of each chiplet and its interconnects affects package resistance, capacitance, thermal performance and signal integrity. Closely spaced dies can reduce distance travelled by signals, but their connections introduce resistance, capacitance and other parasitic effects. Engineers must balance interconnect density and signal integrity with mechanical and thermal behaviour of completed packages. Appropriate construction depends on operating environments and manufacturing costs.
Vehicle electronics add qualification requirements concerning temperature variation, vibration, electrical disturbances and long service periods. Functional safety analysis must consider how failures affecting one chiplet or communication link influence other computing components. These considerations do not establish that chiplet architectures are inherently more reliable; an individual system must be assessed against vehicle application requirements.
BOS develops semiconductor technology for physical AI and automotive applications, including processor architectures intended for advanced computation near equipment using it. The company has reported the tape-out of an AI accelerator and development relationships with automotive manufacturers. Such activities provide background to its selection, although participants have not identified an existing BOS product as the basis of planned interconnect prototypes.
Toyota’s vehicle systems expertise and DENSO’s electronics development experience provide MIRISE with automotive requirements against which candidate interconnects can be assessed. That combination allows semiconductor design decisions to be examined against vehicle requirements at an early stage. The programme can investigate potential arrangements within an automotive context, but neither partner has published measured results or described a completed prototype.
In Europe, the e²LEAD project is also examining automotive chiplet packaging, including power delivery, thermal management and verification. Although the two programmes involve different participants, both investigate the engineering requirements arising when vehicle computing functions occupy several interconnected dies.
The BOS–MIRISE work remains at the research and prototyping stage, with no announced production vehicle, commercial chiplet product, financial value or release date. Further results will need to establish whether the candidate interconnects meet automotive performance, manufacturing and qualification requirements.
