Tenstorrent expands virtual modelling of RISC-V security systems

Tenstorrent and Vayavya Labs have extended their collaboration on SystemC virtual platforms, providing software teams with executable models of security and system management subsystems before corresponding semiconductor hardware becomes available. The latest delivery expands Tenstorrent’s Open Chiplet Harness security enclave processor model and adds further system management capabilities, building on a development relationship established in 2024.

The modelling work covers register complexes within the security enclave processor, system management controller logic, direct memory access engines, secure memory clearing, boot infrastructure, fuse functions and a hardware security module supporting cryptographic operations. Together, these functions control important aspects of how a processor starts, manages privileged operations, moves information and establishes its security state. Their interaction with firmware and operating software must be tested even when physical implementation remains under development.

Vayavya, an Indian engineering company specialising in the interface between semiconductor hardware and software, has developed the models using SystemC and transaction level modelling, commonly abbreviated to TLM. SystemC provides a framework based on C++ for describing and simulating hardware systems, while transaction level modelling represents operations such as register access and data transfer without reproducing every electrical transition occurring inside the eventual circuit.

By modelling register reads and writes as transactions, the SystemC platform lets firmware execute against subsystem behaviour before detailed gate-level models are available. A transaction between a processor and a peripheral can be represented as a read or write operation with defined timing and response characteristics. The model must still reproduce behaviour that software depends upon, including register definitions, access permissions, status changes and error responses.

Precise register behaviour is essential for boot, fuse, security enclave and cryptographic subsystems because early firmware must initialise them in the required order and with appropriate permissions. A hardware security module may handle key related functions or cryptographic operations, depending on implementation, while the virtual platform reproduces the interfaces that software is expected to use.

Direct memory access presents an additional integration challenge because DMA engines transfer information without requiring the processor to execute an instruction for every movement of data. Transactions must respect memory mappings and security restrictions. Tenstorrent’s modelled DMA functions include secure zeroing, which clears information from selected memory regions. A virtual model allows software teams to exercise the control sequences and check expected responses, although it cannot independently establish physical security properties of completed silicon.

Vayavya uses its CSML modelling library and TvastaaVP platform to build the subsystem models in the Accellera SystemC ecosystem. The company provides an open modelling path compatible with the Accellera SystemC ecosystem, alongside a commercial variant configured for Tenstorrent’s simulation environment. Compatibility with established modelling standards allows subsystem representations to be incorporated into larger platforms, provided interfaces and timing assumptions are aligned.

In the latest phase, Vayavya delivered an Open Chiplet Harness security enclave processor virtual platform for two independent simulation targets. Additional system management controller and harness functionality extends the behaviour available to developers. Supporting more than one simulation environment can help identify dependencies on particular tools or integration configurations, although the companies have not disclosed comparative execution speeds, model coverage metrics or software workload sizes.

SystemC transaction level models can execute software more readily than a full register transfer level model because they represent interfaces and behaviour without simulating every logic transition. RTL models describe logic needed to implement a circuit and are used extensively for functional verification, but detailed simulation can become computationally demanding when an entire system is included. Higher level virtual models can execute software more readily by concentrating on interfaces and behaviours necessary for system development. They cannot replace detailed logic verification, timing closure or physical sign-off.

Firmware initially exercised against a virtual controller can later be checked against RTL and physical hardware, revealing discrepancies in register behaviour, access permissions or boot sequences. Maintaining agreement between those representations becomes particularly important as the semiconductor specification changes during development.

Tenstorrent develops RISC-V CPU intellectual property, AI processing cores and computing systems, giving the programme applications beyond a single processor configuration. Company representatives describe earlier access to accurate models as a reason for continuing and expanding the collaboration. The latest deliverables provide additional functionality for software teams before physical silicon is ready, while subsequent validation must establish correspondence with implemented hardware. No specific reduction in development time or completed silicon qualification milestone has been quantified.