IN Brief:
- Applied Materials and Intel will collaborate at the EPIC Center and Oregon research facilities.
- The programme covers advanced logic transistors, materials and semiconductor interconnects.
- Packaging research includes Foveros-based 3D integration, power delivery and thermal performance.
Applied Materials and Intel have expanded their semiconductor research collaboration to address advanced transistor structures, interconnect materials and three-dimensional chip packaging, combining development capabilities at Applied’s EPIC Center in Silicon Valley with Intel’s facilities in Hillsboro, Oregon. The programme covers manufacturing technologies intended for future logic devices and high performance computing systems, including processors designed for demanding artificial intelligence workloads.
The companies have worked together on semiconductor process development for several decades, but the arrangement brings further research into Applied’s Equipment and Process Innovation and Commercialization (EPIC) Center. Intel is a founding partner of the facility, which brings equipment development and device manufacturing research into closer contact. Work will also continue at Intel’s Oregon research campus, where the company develops process technologies for advanced logic manufacturing.
As transistor dimensions become harder to reduce, improving semiconductor performance increasingly depends on changes to device architecture, materials and electrical connections rather than geometric scaling alone. Smaller transistors must retain effective control over current flow while limiting leakage, parasitic resistance and capacitance. At the same time, higher transistor densities place additional demands on metal interconnect networks carrying signals and power across an integrated circuit.
Research will cover the formation of transistors in front-end process stages and the insulating and conducting layers added during back-end-of-line fabrication. Although manufactured in different steps, device structures and interconnects jointly determine leakage, switching behaviour, power distribution and signal propagation in the completed chip.
Electrical resistance within an interconnect increases energy dissipation and can restrict the speed at which signals propagate through a semiconductor design. Capacitance between nearby metal structures adds delay and switching energy, creating a trade-off between routing density and electrical performance. As wiring dimensions decrease, the relative contribution of barrier materials, interfaces and other features can become more important, requiring changes to both processes and materials.
Applied contributes deposition and processing equipment to research on interconnect metals, dielectrics and manufacturing tolerances, while Intel contributes device integration and fabrication expertise. Evaluating the materials and processing steps within a complete manufacturing flow helps identify interactions that would be missed if each layer were developed in isolation.
The collaboration also extends into stacked die packaging compatible with Intel’s Foveros architecture, connecting its transistor and interconnect research to later assembly stages. Foveros enables semiconductor dies to be stacked and interconnected within a package, allowing functions manufactured using different processes to be combined. The engineering challenge includes creating dense electrical connections while distributing power and removing heat from devices positioned in close physical proximity.
Stacking processor and supporting dies changes both the thermal path towards external cooling and the length and density of their electrical connections. Resistance, capacitance and thermal interfaces consequently need to be considered together rather than optimised as unrelated properties of a package.
Applied and Intel intend to investigate higher interconnect density, improved power delivery and better thermal performance for Foveros-based computing platforms. These objectives are related because reducing electrical losses can also decrease heat generation, while thermal management may allow a package to operate within temperature limits. The companies have not released measured improvements in power efficiency, connection pitch, thermal resistance or other parameters arising from this expanded work.
Related hybrid bonding research between Applied Materials and Besi concentrates on assembly processes, while the Intel programme links transistor structures, wiring and package development. Coordinating these stages becomes more demanding as the electrical and physical limits of individual silicon dies increasingly influence system design.
By combining the EPIC Center with Intel’s Oregon research facilities, the companies intend to move candidate processes through development and qualification more efficiently. Intel has likewise linked the programme to demand for computing performance, power efficiency and advanced packaging. Their organisations aim to reduce the time needed to move processes from research into manufacturing, although no specific reduction has been quantified.
The collaboration has not been tied to a named future Intel processor, a particular production node or a confirmed introduction date. Results will depend on material qualification, manufacturing compatibility and the ability to reproduce new structures with the consistency required for semiconductor fabrication. Research across transistor, interconnect and packaging stages provides a route for evaluating those interactions before production adoption.
