Altera unveils Agilex 2X FPGA portfolio

Altera has announced Agilex 2X, a portfolio of four FPGA families covering high-bandwidth computing, communications, industrial control and embedded applications. Agilex 27 is the first family to be introduced, with engineering silicon expected during the second half of 2027 and early software support scheduled to begin in November 2026.

The portfolio includes Agilex 27, 25, 23 and 22, each addressing a different balance of processing performance, connectivity, power consumption and device cost. All four are intended to use a common Quartus Prime development environment, reducing the differences between workflows used for high-end FPGA systems and lower-power embedded designs.

Agilex 27 targets bandwidth-intensive applications including networking infrastructure, radio-frequency signal processing, beamforming and aerospace electronics. Its architecture extends the existing Agilex 7 family with third-generation HyperFlex programmable fabric, additional data-movement resources and support for newer external interfaces.

HyperFlex places registers throughout the programmable routing fabric, allowing design tools to alter the placement of pipeline stages and the timing of signals. This gives the implementation software more opportunities to improve achievable clock frequency while limiting the need to use additional application logic resources solely for pipelining.

Achievable performance nevertheless depends on the structure of the implemented design. Deeply interconnected processing paths, memory access patterns and routing congestion can constrain timing even when individual logic elements support higher operating frequencies. The available registers provide implementation flexibility rather than guaranteeing a particular clock rate.

Altera claims the Agilex 27 architecture can deliver up to 1.8 times the performance per watt of its predecessor generation. That figure describes a manufacturer comparison based on architectural improvements, not an independently measured result for all workloads. Actual performance and power consumption will depend on design configuration, memory traffic, logic utilisation and operating conditions.

The new HyperFlow data network provides a separate architectural change. Distributed across the FPGA, it is designed to move multiple terabits of data per second between internal resources without relying entirely on ordinary programmable logic and routing structures.

Internal data movement can become a limiting factor when a device contains several processing pipelines, high-speed transceivers and memory controllers. Processing blocks may have sufficient arithmetic capacity but remain idle because information cannot be delivered or collected quickly enough. A dedicated transport network can reduce contention for routing resources, although effective throughput will depend on the communication pattern and how a design uses the network.

Agilex 27 also introduces configurable transceivers with speeds up to 256Gbps and hardened support for 800GbE and 1.6TbE Ethernet. Altera has outlined PCI Express 6.0 and 7.0, DDR5, LPDDR5X, LPDDR6, MIPI and UCIe connectivity within the announced family capabilities.

These interfaces address different parts of the system. High-speed transceivers connect the FPGA to external networking equipment and other processors, while memory interfaces support the movement of data between processing blocks and storage. UCIe provides a standardised connection approach for compatible dies within advanced packages, although implementing a functional chiplet system requires additional package and interface engineering.

The other Agilex 2X families have different priorities. Agilex 25 combines high-performance programmable fabric with embedded processing and optimised I/O for systems such as video equipment, drones and low-latency sensors. Agilex 23 targets robotics, industrial automation and automotive systems requiring real-time processing and functional-safety support.

Agilex 22 concentrates on devices with substantial interface and control requirements but less need for high-end computational fabric. Intended applications include board management, motor control, interface bridging and hardware root-of-trust functions, where pin availability, power consumption and predictable operation can be more important than maximum arithmetic throughput.

Across the portfolio, Altera is maintaining common embedded and security foundations, including Arm-based hard processors, Nios V soft processors and secure-device-management functions. The Agilex 27 security architecture includes secure boot, device identity, attestation and protected key management, alongside provisions for adapting cryptographic implementations to future requirements.

Altera has also described line-rate encryption for major data paths, including Ethernet MACsec, PCIe Integrity and Data Encryption and inline memory encryption. These are specific implementation capabilities rather than a guarantee of security for the finished system, which remains dependent on key management, firmware, configuration and the surrounding hardware architecture.

Quartus Prime and the QuartusIQ AI design assistant provide the planned software environment. QuartusIQ is already available in Quartus Prime version 26.3 for supported existing devices, while software support for Agilex 27 is scheduled for early-access customers from mid-November.

The separation between software and hardware availability is substantial. Although customers can begin evaluating development workflows and preparing designs, Agilex 27 engineering samples are not expected until the second half of 2027. Altera has not established equivalent detailed silicon delivery dates for the other three announced families.

The portfolio therefore defines a new FPGA development roadmap, with commercial implementation dependent on completion of device development, silicon qualification, tool support and customer integration. Its initial technical disclosures provide architectural and interface targets, while the performance of completed applications will remain subject to evaluation on physical devices.