ST restructures research leadership across semiconductor technologies

ST restructures research leadership across semiconductor technologies

STMicroelectronics assigns semiconductor research responsibilities across two senior executive roles. Remi El-Ouazzane will become chief technology officer, while Marco Cassis takes the chief strategic officer position from January 2027.


IN Brief:

  • Remi El-Ouazzane will oversee digital CMOS, RF mixed-signal, embedded flash, imaging, advanced packaging and test research.
  • Marco Cassis will lead analogue, power, discrete and MEMS R&D while retaining company strategy responsibilities.
  • The structure takes effect on 1 January 2027, with implementation scheduled through March and revised reporting segments from January.

STMicroelectronics will redistribute semiconductor research responsibilities across two senior executives from 1 January 2027. Remi El-Ouazzane will become chief technology officer, overseeing digital technologies, imaging and advanced packaging research, while Marco Cassis will take the chief strategic officer role alongside leadership of analogue, power and MEMS research. Implementation is scheduled for completion by the end of March 2027.

El-Ouazzane remains president and head of Microcontrollers, Digital ICs, RF and Optical Communication Products and will additionally lead the Imaging Sensors Sub-Group. His technology portfolio will include digital CMOS and associated research into RF mixed-signal circuits, embedded flash memory and imaging. Bringing imaging sensors and digital research under the same executive provides a defined management route for work that connects sensor front ends to on-chip processing and communication interfaces.

Advanced packaging, test and characterisation are also part of the incoming CTO’s remit, together with Global System Research & Applications and System Engineering. The research areas address successive engineering decisions, from device and circuit design to packaged hardware behaviour and system integration. Packaging can impose thermal, electrical and interconnect constraints that feed back into silicon design, while characterisation checks whether fabricated devices behave within the intended operating envelope.

ST says the allocation is intended to improve coordination between research, product development and technology activities. System design often brings together functional blocks that progress on different engineering schedules: a sensing element, a digital processing die, memory and a communications interface may each have distinct qualification requirements. A single technology reporting line may simplify the escalation of shared design questions, although the organisation has given no revised product milestones or performance measurements arising from the changes.

Cassis will continue as president of Analog, Power & Discrete and MEMS Products and take direct responsibility for research in those technologies. He also retains responsibility for ST’s strategy, with his new chief strategic officer title covering the alignment of business objectives with market developments, partnerships and potential acquisitions. His R&D remit remains distinct from El-Ouazzane’s digital research portfolio, reflecting the company’s separate product areas.

Power devices and analogue components frequently require different process capabilities and validation methods from digital CMOS logic. High-voltage insulation, power dissipation, sensing structures and long operational life can shape both device design and packaging. MEMS products add mechanical structures and associated manufacturing processes, while analogue circuits may be integrated with digital functions in mixed-signal devices. The new responsibilities specify who leads the technology groups without prescribing a new device architecture.

The two research portfolios meet in products containing several semiconductor technologies. An industrial sensor module, for example, can combine a MEMS sensing element, analogue signal conditioning, digital processing and nonvolatile memory in a single assembly. Development across such boundaries requires agreement on interfaces, electrical characteristics and test coverage. ST’s new leadership structure places accountability for the respective technology areas, while the detailed coordination arrangements will be established as implementation progresses.

Chief executive Jean-Marc Chery remains in post, and ST says the remaining organisation is unchanged. The reorganisation’s effective date precedes the end of its implementation period by three months, allowing the handover of research responsibilities and management arrangements to continue into the first quarter of 2027. Reportable business segments will be adjusted from January, creating a separate reporting consequence alongside the research-management changes.

Packaging and system engineering connect the digital and analogue portfolios despite differences in their qualification programmes. A digital process choice can influence memory and RF integration, while power and sensor products can impose specialised reliability requirements. Packaging, test and system engineering can connect the portfolios even where product and manufacturing methods differ. The expanded CTO and CSO responsibilities establish named ownership for those decisions, with subsequent technology roadmaps determining the practical sequence of work.

The new responsibilities take effect on 1 January 2027, with the transfer of duties scheduled for completion by the end of March. ST’s stated changes concern technology leadership, research and reporting arrangements; the company’s existing product development programmes continue through the transition. Product programmes will continue under the company’s existing semiconductor businesses, with the research reporting lines adjusted around them.


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