IN Brief:
- Each JESD204C core supports eight lanes at up to 32 Gbps, providing 256 Gbps aggregate serial line rate.
- Four cores can provide up to 1 Tbps of aggregate connectivity with deterministic latency and JESD204B compatibility.
- Speedster7t combines 112 Gbps SerDes, GDDR6 controllers, PCIe Gen5, and a 2D network-on-chip for high-rate converter systems.
Achronix Semiconductor has released a JESD204C intellectual-property core for its Speedster7t FPGA family, providing a standards-based interface between programmable logic and high-speed analogue-to-digital and digital-to-analogue converters. Each core supports data rates up to 32 Gbps per lane and eight lanes per link, giving an aggregate serial line rate of 256 Gbps.
Designs can combine four cores to provide aggregate connectivity of up to 1 Tbps. The IP supports both JESD204C and JESD204B converters, allowing systems based on established devices to retain their converter hardware while moving the programmable-logic side towards the newer interface standard.
The core supports 64b/66b and 8b/10b encoding, forward error correction, CRC-12 and CRC-3 modes, while Subclass 1 operation provides deterministic latency for single- and multi-channel systems. An AXI-Lite interface handles control, and the IP includes alignment and recovery functions intended to simplify integration into wider signal-processing architectures.
Deterministic latency is particularly important where several converter channels have to preserve a known timing relationship. Radar receivers, phased-array radios, high-bandwidth test equipment, and imaging systems may divide analogue inputs across multiple converters and serial lanes, but later digital processing depends on maintaining consistent alignment between those channels after startup or a link reset.
JESD204C also reduces the number of physical connections required between converters and processing devices compared with wide parallel interfaces. Fewer high-speed serial lanes can simplify PCB routing and package pin allocation, although the engineering burden shifts towards SerDes signal integrity, reference-clock quality, power integrity, and careful control of board losses and discontinuities.
At 32 Gbps per lane, trace geometry, vias, connectors, package transitions, and PCB materials can all affect the available signal margin. Faster serial transport therefore removes some layout congestion while placing greater emphasis on the quality of the remaining high-speed paths.
Achronix is coupling the converter interface with the existing high-bandwidth resources inside Speedster7t. The FPGA family provides SerDes capable of operating at up to 112 Gbps and uses a two-dimensional network-on-chip to move traffic between external interfaces, memory controllers, and programmable logic without relying entirely on conventional FPGA routing.
The devices also integrate up to eight GDDR6 memory controllers, providing as much as 4 Tbps of aggregate memory bandwidth. High-speed converter systems often need substantial buffering because incoming samples cannot always be consumed immediately by downstream processing. Data may have to be reordered, windowed, accumulated, or retained while algorithms operate across multiple channels.
Embedded machine-learning processors provide additional resources for DSP and inference close to the acquired data, while PCI Express Gen5 interfaces provide a path into host systems. That combination allows incoming converter traffic to pass through serial acquisition, local buffering, signal processing, and host transfer without every stage competing for the same programmable interconnect.
The JESD204C core itself is supplied as synthesizable VHDL and Verilog and is integrated into the Achronix ACE design environment through a graphical interface. The package includes templates, example designs, simulation tools, testbenches, and configuration scripts for VectorPath accelerator cards.
Achronix has previously demonstrated its JESD204C implementation using a VectorPath 815 card and an Analog Devices AD9082 mixed-signal front end. That laboratory system operated four serial lanes at 24.75 Gbps, the maximum data rate supported by the converter used in the demonstration, while the Speedster7t SerDes was capable of supporting the 32 Gbps upper rate specified by JESD204C.
The newly available IP takes that capability from a reference implementation into a supported design package. The practical limit in many systems will now move beyond the converter link itself towards memory bandwidth, processing resources, clock distribution, and PCB implementation as channel counts and sample rates continue to increase.
