IN Brief:
- FlexGen Multi-Die carries NoC transactions, virtual channels, and quality-of-service behaviour across die-to-die links.
- Bidirectional traffic can use one UCIe PHY, which Arteris says can cut PHY area, power, and I/O requirements by up to 50%.
- The product complements coherent Ncore Multi-Die technology and targets AI and HPC systems divided across several chiplets.
Arteris has extended its network-on-chip technology across die boundaries with FlexGen Multi-Die, targeting AI and high-performance computing devices that divide processing, memory, and other system functions between several chiplets rather than implementing the complete architecture on one monolithic die.
The new IP carries NoC transactions across die-to-die links while preserving traffic-management features including virtual channels and quality of service. FlexGen Multi-Die is aimed at non-coherent architectures, while Arteris’ Ncore Multi-Die technology addresses systems where caches and processors require coherent access to shared memory.
One of the more specific changes concerns the physical chiplet interface. FlexGen Multi-Die supports bidirectional transactions through a single UCIe PHY. Arteris says this can reduce PHY area, power, and I/O requirements by up to 50% compared with an architecture that allocates separate physical resources to each traffic direction.
The claim addresses a practical constraint in multi-die design. Chiplets can improve manufacturing yield, allow different process technologies to be combined, and make large processors easier to partition, but package-edge I/O is not unlimited. Every additional die-to-die link consumes area, power, routing resources, and package connections that might otherwise be available to memory or other interfaces.
Within a conventional monolithic SoC, the NoC already determines how CPUs, accelerators, memory interfaces, peripherals, and other blocks exchange data. Moving some of those functions onto separate dies does not remove the communication architecture; it inserts physical links into the middle of it.
Standards such as UCIe provide mechanisms for moving data between dies, while other designs may use BoW or proprietary PHYs. Arteris works above those physical connections, transporting standard interfaces and system traffic through the NoC so that architects do not have to treat every chiplet boundary as a completely separate subsystem.
That distinction becomes more important as the number of dies increases. A simple two-chip package can tolerate a relatively direct bridge between functions, but an AI accelerator assembled from many compute tiles and I/O chiplets can generate several classes of traffic with different latency, ordering, and bandwidth requirements.
FlexGen Multi-Die uses virtual-channel link technology to allow logical traffic flows to share constrained chiplet I/O. Quality-of-service mechanisms can prioritise transactions that cannot tolerate congestion, helping architects preserve some of the behaviour established within the original NoC when data has to cross a package boundary.
The approach does not make the boundary disappear. UCIe bandwidth, propagation latency, buffering, clock-domain crossings, package routing, power states, thermal constraints, and link failures still create physical differences between an on-die path and an off-die transaction. The purpose of the interconnect layer is to make those differences manageable without rewriting the complete architecture every time the design is partitioned.
Verification becomes correspondingly more difficult in a multi-die system. Engineers have to consider link initialisation, resets, ordering, congestion, degraded paths, power-state changes, unavailable chiplets, and combinations of traffic that may not exist in a monolithic version. End-to-end latency can also change depending on where blocks are physically placed within the package.
Arteris combines its NoC products with Magillem integration automation, and the wider multi-die platform supports standard interfaces including Arm AMBA AXI and CXS together with UCIe, BoW, and proprietary die-to-die technologies. That provides system designers with a path from logical interconnect planning through the integration work surrounding multiple dies.
The company already has FlexGen adoption in chiplet programmes. AMD has licensed the technology for next-generation designs, while Arteris has previously described multi-die deployments across automotive and other processing architectures. The latest development extends the transport model itself across the physical boundary rather than using FlexGen only within each individual chiplet.
Recent custom compute programmes are also treating chiplets as routine building blocks for AI and high-performance silicon, increasing demand for interconnect IP and design automation that can handle partitioned systems without multiplying integration work.
FlexGen Multi-Die is therefore less about adding another die-to-die PHY than about preserving system-level traffic behaviour across whichever compatible physical link a design uses. That distinction will become more valuable if multi-vendor chiplets become practical, because the package will need a predictable way to transport and prioritise transactions even when individual dies have been designed by different organisations.
The real test will come in physical implementation. Sharing one PHY and maintaining virtual channels may reduce interface overhead, but system architects still have to balance bandwidth, latency, package area, power, verification complexity, and failure handling. Chiplets make it easier to divide silicon; technologies such as FlexGen Multi-Die are being developed to stop that division turning one SoC integration problem into several disconnected ones.